Datasheet

Time (5 s/div)μ
Trigger (5 V/div)LDAC
Large Signal V (1 V/div)
OUT
Small Signal Settling (0.61 mV/div = 0.024% FSR)
From Code:
To Code:
4000h
C000h
Time (5 s/div)μ
Trigger (5 V/div)LDAC
Large Signal V (1 V/div)
OUT
Small Signal Settling (0.61 mV/div = 0.024% FSR)
From Code: C000h
To Code: 4000h
Time (5 s/div)μ
Trigger (5 V/div)LDAC
Large Signal V (1 V/div)
OUT
Small Signal Settling (0.61 mV/div = 0.024% FSR)
From Code:
To Code:
0h
FFFFh
Time (5 s/div)μ
Trigger (5 V/div)LDAC
Large Signal V (1 V/div)
OUT
Small Signal Settling (0.61 mV/div = 0.024% FSR)
From Code: FFFF
To Code: 0
h
h
−1
0
1
2
3
4
−20 −15 −10 −5 0 5 10 15 20
I
LOAD
(mA)
Output Voltage (V)
Full scale
Mid scale
Zero scale
Typical channel shown
0.0
0.5
1.0
1.5
2.0
2.5
3.0
−40 −25 −10 5 20 35 50 65 80 95 110 125
Temperature (°C)
Power−Down Current (µA)
G073
DAC8562, DAC8563
DAC8162, DAC8163
DAC7562, DAC7563
www.ti.com SLAS719D –AUGUST 2010–REVISED AUGUST 2012
TYPICAL CHARACTERISTICS: DAC at AV
DD
= 2.7 V (continued)
At T
A
= 25°C, 2.5-V external reference used, gain = 1 and DAC output not loaded, unless otherwise noted.
POWER-DOWN CURRENT DAC OUTPUT VOLTAGE
vs TEMPERATURE vs LOAD CURRENT
Figure 73. Figure 74.
FULL-SCALE SETTLING TIME: FULL-SCALE SETTLING TIME:
RISING EDGE FALLING EDGE
Figure 75. Figure 76.
HALF-SCALE SETTLING TIME: HALF-SCALE SETTLING TIME:
RISING EDGE FALLING EDGE
Figure 77. Figure 78.
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