Datasheet

Time (1 ms/div)
AV (2 V/div)
DD
V A (50 mV/div)
OUT
V shorted to
REFIN
AV
DD
V B (50 mV/div)
OUT
Time (1 ms/div)
AV (2 V/div)
DD
V A (1 V/div)
OUT
V shorted to
REFIN
AV
DD
V B (1 V/div)
OUT
Time (5 s/div)μ
Trigger (5 V/div)LDAC
Large Signal V (2 V/div)
OUT
Small Signal Settling (1.22 mV/div = 0.024% FSR)
From Code:
To Code:
4000h
C000h
Time (5 s/div)μ
Trigger (5 V/div)LDAC
Large Signal V (2 V/div)
OUT
Small Signal Settling (1.22 mV/div = 0.024% FSR)
From Code: C000h
To Code: 4000h
Time (5 s/div)μ
Trigger (5 V/div)LDAC
Large Signal V (2 V/div)
OUT
Small Signal Settling
(1.22 mV/div = 0.024% FSR)
From Code:
To Code:
0h
FFFFh
Time (5 s/div)μ
Trigger (5 V/div)LDAC
Large Signal V (2 V/div)
OUT
Small Signal Settling (1.22 mV/div = 0.024% FSR)
From Code: FFFF
To Code: 0
h
h
DAC8562, DAC8563
DAC8162, DAC8163
DAC7562, DAC7563
SLAS719D AUGUST 2010REVISED AUGUST 2012
www.ti.com
TYPICAL CHARACTERISTICS: DAC at AV
DD
= 5.5 V (continued)
At T
A
= 25°C, 5-V external reference used, gain = 1 and DAC output not loaded, unless otherwise noted.
FULL-SCALE SETTLING TIME: FULL-SCALE SETTLING TIME:
RISING EDGE FALLING EDGE
Figure 31. Figure 32.
HALF-SCALE SETTLING TIME: HALF-SCALE SETTLING TIME:
RISING EDGE FALLING EDGE
Figure 33. Figure 34.
POWER-ON GLITCH POWER-ON GLITCH
RESET TO ZERO SCALE RESET TO MIDSCALE
Figure 35. Figure 36.
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