Datasheet

DAC8565
www.ti.com SBAS411C –JUNE 2007–REVISED MARCH 2011
SERIAL INTERFACE consumption of the device, care should be taken that
the levels are as close to each rail as possible. Refer
The DAC8565 has a 3-wire serial interface (SYNC,
to the Typical Characteristics section for Figure 36,
SCLK, and D
IN
) compatible with SPI, QSPI, and
Figure 57, and Figure 79 (Supply Current vs Logic
Microwire interface standards, as well as most DSPs.
Input Voltage).
See the Serial Write Operation timing diagram for an
example of a typical write sequence.
IOV
DD
AND VOLTAGE TRANSLATORS
The DAC8565 input shift register is 24 bits wide,
The IOV
DD
pin powers the the digital input structures
consisting of eight control bits (DB23 to DB16) and 16
of the DAC8565. For single-supply operation, it can
data bits (DB15 to DB0). All 24 bits of data are
be tied to AV
DD
. For dual-supply operation, the IOV
DD
loaded into the DAC under the control of the serial
pin provides interface flexibility with various CMOS
clock input, SCLK. DB23 (MSB) is the first bit that is
logic families and should be connected to the logic
loaded into the DAC shift register, and is followed by
supply of the system. Analog circuits and internal
the rest of the 24-bit word pattern, left-aligned. This
logic of the DAC8565 use AV
DD
as the supply
configuration means that the first 24 bits of data are
voltage. The external logic high inputs translate to
latched into the shift register and any further clocking
AV
DD
by level shifters. These level shifters use the
of data is ignored. The DAC8565 receives all 24 bits
IOV
DD
voltage as a reference to shift the incoming
of data and decodes the first eight bits to determine
logic HIGH levels to AV
DD
. IOV
DD
is ensured to
the DAC operating/control mode. The 16 bits of data
operate from 2.7V to 5.5V regardless of the AV
DD
that follow are decoded by the DAC to determine the
voltage, assuring compatibility with various logic
equivalent analog output. The data format is straight
families. Although specified down to 2.7V, IOV
DD
binary with all '0's corresponding to 0V output and all
operates at as low as 1.8V with degraded timing and
'1's corresponding to full-scale output (that is, V
REF
–
temperature performance. For lowest power
1 LSB); see the Data Format section for more details.
consumption, logic V
IH
levels should be as close as
The write sequence begins by bringing the SYNC line possible to IOV
DD
, and logic V
IL
levels should be as
low. Data from the D
IN
line are clocked into the 24-bit close as possible to GND voltages.
shift register on each falling edge of SCLK. The serial
clock frequency can be as high as 50MHz, making
ASYNCHRONOUS RESET
the DAC8565 compatible with high-speed DSPs. On
The DAC8565 output is asynchronously set to
the 24th falling edge of the serial clock, the last data
zero-scale voltage or midscale voltage (depending on
bit is clocked into the shift register and the shift
RSTSEL) immediately after the RST pin is brought
register locks. Further clocking does not change the
low. The RST signal resets all internal registers, and
shift register data. Once 24 bits are locked into the
therefore, behaves like the Power-On Reset. The
shift register, the eight MSBs are used as control bits
RST pin must be brought back to high before a write
and the 16 LSBs are used as data. After receiving the
sequence starts. If the RSTSEL pin is high, the RST
24th falling clock edge, the DAC8565 decodes the
signal going low resets all outputs to midscale. If the
eight control bits and 16 data bits to perform the
RSTSEL pin is low, the RST signal going low resets
required function, without waiting for a SYNC rising
all outputs to zero-scale. RSTSEL should be set at
edge. A new write sequence starts at the next falling
power-up.
edge of SYNC. A rising edge of SYNC before the
24-bit sequence is complete resets the SPI interface;
INPUT SHIFT REGISTER
no data transfer occurs. After the 24th falling edge of
SCLK is received, the SYNC line may be kept LOW
The input shift register (SR) of the DAC8565 is 24
or brought HIGH. In either case, the minimum delay
bits wide, as shown in Table 5. It consists of eight
time from the 24th falling SCLK edge to the next
control bits (DB23 to DB16) and 16 data bits (DB15
falling SYNC edge must be met in order to properly
to DB0). DB23 and DB22 should always be '0'.
begin the next cycle. To assure the lowest power
Table 5. DAC8565 Data Input Register Format
DB23 DB12
0 0 LD1 LD0 0 DAC Select 1 DAC Select 0 PD0 D15 D14 D13 D12
DB11 DB0
D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
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