Datasheet

DAC
Register
REF(+)
ResistorString
REF( )-
V L
REF
V H
REF
V
OUT
X
62kW
50kW 50kW
V
OUT
X + 2 V
REF
L )
(
V
REF
H * V
REF
L
)
D
IN
65536
V
REF
R
R
R
R
V
REF
2
R
DIVIDER
ToOutputAmplifier
(2xGain)
DAC8565
www.ti.com SBAS411C –JUNE 2007–REVISED MARCH 2011
THEORY OF OPERATION
DIGITAL-TO-ANALOG CONVERTER (DAC) code loaded into the DAC register determines at
which node on the string the voltage is tapped off to
The DAC8565 architecture consists of a string DAC
be fed into the output amplifier by closing one of the
followed by an output buffer amplifier. Figure 92
switches connecting the string to the amplifier. It is
shows a block diagram of the DAC architecture.
monotonic because it is a string of resistors.
Figure 92. DAC8565 Architecture
The input coding to the DAC8565 can be straight
binary or two's complement, so the ideal output
voltage is given by Equation 1.
(1)
where D
IN
= decimal equivalent of the binary code
that is loaded to the DAC register; it can range from 0
to 65535. X represents channel A, B, C, or D.
DATA FORMAT
The data format can be straight binary or two’s
complement. Table 1 illustrates the differences
between USB (unsigned straight binary) and BTC
(binary two’s complement) data formats.
Table 1. USB and BTC Codes
USB CODE BTC CODE DESCRIPTION
FFFFh 7FFFh +Full-Scale – 1LSB
Figure 93. Resistor String
...
8001h 0001h Midscale + 1LSB
8000h 0000h Midscale
OUTPUT AMPLIFIER
7FFFh FFFFh Midscale – 1LSB
The output buffer amplifier is capable of generating
...
rail-to-rail voltages on its output, giving an output
0000h 8000h Zero Scale
range of 0V to AV
DD
. It is capable of driving a load of
2kΩ in parallel with 1000pF to GND. The source and
sink capabilities of the output amplifier can be seen in
RESISTOR STRING
the Typical Characteristics. The slew rate is 2.2V/μs,
The resistor string section is shown in Figure 93. It is
with a full-scale settling time of 8μs with the output
simply a string of resistors, each of value R. The
unloaded.
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