Datasheet

DAC8564
www.ti.com SBAS403D –JUNE 2007–REVISED MAY 2011
SERIAL INTERFACE begin the next cycle. To assure the lowest power
consumption of the device, care should be taken that
The DAC8564 has a 3-wire serial interface (SYNC,
the levels are as close to each rail as possible. Refer
SCLK, and D
IN
) compatible with SPI, QSPI, and
to the Typical Characteristics section for Figure 36,
Microwire interface standards, as well as most DSPs.
Figure 57, and Figure 79 (Supply Current vs Logic
See the Serial Write Operation timing diagram for an
Input Voltage).
example of a typical write sequence.
The DAC8564 input shift register is 24 bits wide, IOV
DD
AND VOLTAGE TRANSLATORS
consisting of eight control bits (DB23 to DB16) and 16
The IOV
DD
pin powers the digital input structures of
data bits (DB15 to DB0). All 24 bits of data are
the DAC8564. For single-supply operation, it can be
loaded into the DAC under the control of the serial
tied to AV
DD
. For dual-supply operation, the IOV
DD
pin
clock input, SCLK. DB23 (MSB) is the first bit that is
provides interface flexibility with various CMOS logic
loaded into the DAC shift register, and is followed by
families and should be connected to the logic supply
the rest of the 24-bit word pattern, left-aligned. This
of the system. Analog circuits and internal logic of the
configuration means that the first 24 bits of data are
DAC8564 use AV
DD
as the supply voltage. The
latched into the shift register and any further clocking
external logic high inputs translate to AV
DD
by level
of data is ignored. The DAC8564 receives all 24 bits
shifters. These level shifters use the IOV
DD
voltage as
of data and decodes the first eight bits to determine
a reference to shift the incoming logic HIGH levels to
the DAC operating/control mode. The 16 bits of data
AV
DD
. IOV
DD
is ensured to operate from 2.7V to 5.5V
that follow are decoded by the DAC to determine the
regardless of the AV
DD
voltage, assuring compatibility
equivalent analog output. The data format is straight
with various logic families. Although specified down to
binary with all '0's corresponding to 0V output and all
2.7V, IOV
DD
operates at as low as 1.8V with
'1's corresponding to full-scale output (that is, V
REF
–
degraded timing and temperature performance. For
1 LSB).
lowest power consumption, logic V
IH
levels should be
The write sequence begins by bringing the SYNC line as close as possible to IOV
DD
, and logic V
IL
levels
low. Data from the D
IN
line are clocked into the 24-bit should be as close as possible to GND voltages.
shift register on each falling edge of SCLK. The serial
clock frequency can be as high as 50MHz, making
INPUT SHIFT REGISTER
the DAC8564 compatible with high-speed DSPs. On
The input shift register (SR) of the DAC8564 is 24
the 24th falling edge of the serial clock, the last data
bits wide, as shown in Table 4, and consists of eight
bit is clocked into the shift register and the shift
control bits (DB23 and DB16) and 16 data bits (DB15
register locks. Further clocking does not change the
to DB0). The first two control bits (DB23 and DB22)
shift register data. Once 24 bits are locked into the
are the address match bits. The DAC8564 offers
shift register, the eight MSBs are used as control bits
hardware-enabled addressing capability, allowing a
and the 16 LSBs are used as data. After receiving the
single host to talk to up to four DAC8564s through a
24th falling clock edge, the DAC8564 decodes the
single SPI bus without any glue logic, enabling up to
eight control bits and 16 data bits to perform the
16-channel operation. The state of DB23 should
required function, without waiting for a SYNC rising
match the state of pin A1; similarly, the state of DB22
edge. A new write sequence starts at the next falling
should match the state of pin A0. If there is no match,
edge of SYNC. A rising edge of SYNC before the
the control command and the data (DB21...DB0) are
24-bit sequence is complete resets the SPI interface;
ignored by the DAC8564. That is, if there is no
no data transfer occurs. After the 24th falling edge of
match, the DAC8564 is not addressed. Address
SCLK is received, the SYNC line may be kept LOW
matching can be overridden by the broadcast update.
or brought HIGH. In either case, the minimum delay
time from the 24th falling SCLK edge to the next
falling SYNC edge must be met in order to properly
Table 4. Data Input Register Format
DB23 DB12
A1 A0 LD1 LD0 0 DAC Select 1 DAC Select 0 PD0 D15 D14 D13 D12
DB11 DB0
D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
Copyright © 2007–2011, Texas Instruments Incorporated 29