Datasheet

0.70

0.00

AV (

5.50

2.20

2.70

Specified Supply

Voltage Range

No Power-On Reset

Power-On Reset

Undefined

DAC8562, DAC8563

DAC8162, DAC8163

DAC7562, DAC7563

SLAS719D –AUGUST 2010–REVISED AUGUST 2012

www.ti.com

Power-On Reset (POR) Levels

When the device powers up, a POR circuit sets the device in default mode as shown in Table 6. The POR circuit

requires specific AV

levels, as indicated in Figure 91, to ensure discharging of internal capacitors and to reset

the device on power up. In order to ensure a power-on reset, AV

must be below 0.7 V for at least 1 ms. When

drops below 2.2 V but remains above 0.7 V (shown as the undefined region), the device may or may not

reset under all specified temperature and power-supply conditions. In this case, TI recommends a power-on

reset. When AV

remains above 2.2 V, a power-on reset does not occur.

Figure 91. Relevant Voltage Levels for POR Circuit

CLR FUNCTIONALITY

The edge-triggered CLR pin can be used to set the input and DAC registers immediately according to Table 7.

When the CLR pin receives a falling edge signal the clear mode is activated and changes the DAC output

voltages accordingly. The part exits clear mode on the 24

falling edge of the next write to the part. If the CLR

pin receives a falling edge signal during a write sequence in normal operation, the clear mode is activated and

changes the input and DAC registers immediately according to Table 7.

Table 7. Clear Mode Reset Values

DEVICE DAC Output Entering Clear Mode

DAC8562, DAC8162, DAC7562 Zero-scale

DAC8563, DAC8163, DAC7563 Mid-scale

Product Folder Links: DAC8562 DAC8563 DAC8162 DAC8163 DAC7562 DAC7563