Datasheet

SCLK 1 24
SYNC
D
IN
DB23
DB0
DB23
t
10
t
6
t
3
t
2
t
1
t
7
t
9
t
5
t
4
t
8
DAC8560
SLAS464B –DECEMBER 2006–REVISED NOVEMBER 2011 www.ti.com
SERIAL WRITE OPERATION
TIMING REQUIREMENTS
(1) (2)
V
DD
= 2.7V to 5.5V, all specifications –40°C to +105°C (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
V
DD
= 2.7V to 3.6V 50
t
1
(3)
SCLK cycle time ns
V
DD
= 3.6V to 5.5V 33
V
DD
= 2.7V to 3.6V 13
t
2
SCLK HIGH time ns
V
DD
= 3.6V to 5.5V 13
V
DD
= 2.7V to 3.6V 22.5
t
3
SCLK LOW time ns
V
DD
= 3.6V to 5.5V 13
V
DD
= 2.7V to 3.6V 0
t
4
SYNC to SCLK rising edge setup time ns
V
DD
= 3.6V to 5.5V 0
V
DD
= 2.7V to 3.6V 5
t
5
Data setup time ns
V
DD
= 3.6V to 5.5V 5
V
DD
= 2.7V to 3.6V 4.5
t
6
Data hold time ns
V
DD
= 3.6V to 5.5V 4.5
V
DD
= 2.7V to 3.6V 0
t
7
SCLK falling edge to SYNC rising edge ns
V
DD
= 3.6V to 5.5V 0
V
DD
= 2.7V to 3.6V 50
t
8
Minimum SYNC HIGH time ns
V
DD
= 3.6V to 5.5V 33
V
DD
= 2.7V to 3.6V 100
t
9
24th SCLK falling edge to SYNC falling edge ns
V
DD
= 3.6V to 5.5V 100
V
DD
= 2.7V to 3.6V 15
SYNC rising edge to 24th SCLK falling edge
t
10
ns
(for successful SYNC interrupt)
V
DD
= 3.6V to 5.5V 15
(1) All input signals are specified with t
R
= t
F
= 3ns (10% to 90% of V
DD
) and timed from a voltage level of (V
IL
+ V
IH
)/2.
(2) See Serial Write Operation timing diagram.
(3) Maximum SCLK frequency is 30MHz at V
DD
= 3.6V to 5.5V and 20MHz at V
DD
= 2.7V to 3.6V.
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