Datasheet

SYNC
SCLK
D
IN
Microwire
TM
CS
SK
SO
DAC8560
(1)
NOTE: (1) Additional pins omitted for clarity.
68HC11
(1)
PC7
SCK
MOSI
SYNC
SCLK
D
IN
(1)
NOTE: (1) Additional pins omitted for clarity.
DAC8560
80C51/80L51
(1)
P3.3
TXD
RXD
(1)
SYNC
SCLK
D
IN
NOTE: (1) Additional pins omitted for clarity.
DAC8560
DAC8560
SLAS464B –DECEMBER 2006–REVISED NOVEMBER 2011 www.ti.com
MICROPROCESSOR INTERFACING
DAC8560 TO 8051 Interface
See Figure 71 for a serial interface between the
DAC8560 and a typical 8051-type microcontroller.
The setup for the interface is as follows: TXD of the
8051 drives SCLK of the DAC8560, while RXD drives
the serial data line of the device. The SYNC signal is
Figure 72. DAC8560 to Microwire Interface
derived from a bit-programmable pin on the port of
the 8051. In this case, port line P3.3 is used. When
data is to be transmitted to the DAC8560, P3.3 is
DAC8560 to 68HC11 Interface
taken LOW. The 8051 transmits data in 8-bit bytes;
Figure 73 shows a serial interface between the
thus, only eight falling clock edges occur in the
DAC8560 and the 68HC11 microcontroller. SCK of
transmit cycle. To load data to the DAC, P3.3 is left
the 68HC11 drives the SCLK of the DAC8560, while
LOW after the first eight bits are transmitted, then a
the MOSI output drives the serial data line of the
second write cycle is initiated to transmit the second
DAC. The SYNC signal is derived from a port line
byte of data. P3.3 is taken HIGH following the
(PC7), similar to the 8051 diagram.
completion of the third write cycle. The 8051 outputs
the serial data in a format which has the LSB first.
The DAC8560 requires its data with the MSB as the
first bit received. The 8051 transmit routine must
therefore take this into account, and mirror the data
as needed.
Figure 73. DAC8560 to 68HC11 Interface
The 68HC11 should be configured so that its CPOL
bit is '0' and its CPHA bit is '1'. This configuration
causes data appearing on the MOSI output to be
valid on the falling edge of SCK. When data is being
Figure 71. DAC8560 to 80C51/80L51 Interface
transmitted to the DAC, the SYNC line is held LOW
(PC7). Serial data from the 68HC11 is transmitted in
DAC8560 to Microwire Interface
8-bit bytes with only eight falling clock edges
occurring in the transmit cycle. (Data is transmitted
Figure 72 shows an interface between the DAC8560
MSB first.) In order to load data to the DAC8560,
and any Microwire compatible device. Serial data is
PC7 is left LOW after the first eight bits are
shifted out on the falling edge of the serial clock and
transferred, then a second and third serial write
is clocked into the DAC8560 on the rising edge of the
operation is performed to the DAC. PC7 is taken
SK signal.
HIGH at the end of this procedure.
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