Datasheet

CLK
SYNC
D
IN
ValidWriteSequence:
Output/ModeUpdates onthe24thFallingEdge
24thFallingEdge 24thFallingEdge
DB23 DB0 DB23 DB0
Invalid/InterruptedWriteSequence:
Output/ModeDoesNotUpdate onthe24thFallingEdge
DAC8560
SLAS464B –DECEMBER 2006–REVISED NOVEMBER 2011 www.ti.com
SERIAL INTERFACE A more complete description of the various modes is
located in the Power-Down Modes section. The next
The DAC8560 has a 3-wire serial interface ( SYNC,
16 bits are the data bits, which are transferred to the
SCLK, and D
IN
) that is compatible with SPI, QSPI,
DAC register on the 24th falling edge of SCLK under
and Microwire interface standards, as well as most
normal operation (see Table 5).
DSPs. See the Serial Write Operation timing diagram
for an example of a typical write sequence.
SYNC INTERRUPT
The write sequence begins by bringing the SYNC line
In a normal write sequence, the SYNC line is kept
LOW. Data from the D
IN
line is clocked into the 24-bit
LOW for at least 24 falling edges of SCLK and the
shift register on each falling edge of SCLK. The serial
DAC is updated on the 24th falling edge. However, if
clock frequency can be as high as 30MHz, making
SYNC is brought HIGH before the 24th falling edge, it
the DAC8560 compatible with high-speed DSPs. On
acts as an interrupt to the write sequence. The shift
the 24th falling edge of the serial clock, the last data
register is reset, and the write sequence is seen as
bit is clocked in and the programmed function is
invalid. Neither an update of the DAC register
executed.
contents, nor a change in the operating mode occurs,
At this point, the SYNC line may be kept LOW or as shown in Figure 65.
brought HIGH. In either case, it must be brought
HIGH for a minimum of 33ns before the next write
POWER-ON RESET
sequence so that a falling edge of SYNC can initiate
The DAC8560 contains a power-on-reset circuit that
the next write sequence. As previously mentioned, it
controls the output voltage during power up. On
must be brought HIGH again before the next write
power up, all registers are filled with zeros and the
sequence.
output voltage is zero-scale; it remains there until a
valid write sequence is made to the DAC. This
INPUT SHIFT REGISTER
feature is useful in applications where it is important
The input shift register is 24 bits wide, as shown in to know the state of the output of the DAC while it is
Table 4. The first six bits must be '000000'. The next in the process of powering up.
two bits (PD1 and PD0) are control bits that set the
desired mode of operation (normal mode or any one
of three power-down modes) as indicated in Table 5.
Table 4. DAC8560 Data Input Register Format
DB23 DB0
0 0 0 0 0 0 PD PD D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
1 0
Figure 65. SYNC Interrupt Facility
20 Submit Documentation Feedback Copyright © 2006–2011, Texas Instruments Incorporated
Product Folder Link(s): DAC8560