Datasheet

V
REF
R
1
1 Q
2
NQ
1
R
2
Reference
Disable
DAC8560
www.ti.com SLAS464B –DECEMBER 2006– REVISED NOVEMBER 2011
INTERNAL REFERENCE
The DAC8560 includes a 2.5V internal reference that
is enabled by default. The internal reference is
externally available at the V
REF
pin. A minimum
100nF capacitor is recommended between the
reference output and GND for noise filtering.
The internal reference of the DAC8560 is a bipolar
transistor-based, precision bandgap voltage
reference. The basic bandgap topology is shown in
Figure 64. Transistors Q
1
and Q
2
are biased such
that the current density of Q
1
is greater than that of
Q
2
. The difference of the two base-emitter voltages
(V
BE1
- V
BE2
) has a positive temperature coefficient
and is forced across resistor R
1
. This voltage is
gained up and added to the base-emitter voltage of
Q
2
, which has a negative temperature coefficient. The
Figure 64. Simplified Schematic of the Bandgap
resulting output voltage is virtually independent of
Reference
temperature. The short-circuit current is limited by
design to approximately 100mA.
Enable/Disable Internal Reference
The DAC8560 internal reference is enabled by To then enable the reference, either perform a
default; however, the reference can be disabled for power-cycle to reset the device, or sequentially
debugging or evaluation purposes. A serial command execute the two write sequences in Table 2 and
requiring at least two additional SCLK cycles at the Table 3. Each of these write sequences must be
end of the 24-bit write sequence (see Serial Interface followed by at least two additional SCLK falling edges
section) must be used to disable the internal while SYNC remains low.
reference. For proper operation, a total of at least 26
During the time that the internal reference is disabled,
SCLK cycles are required for each enable/disable
the DAC will function normally using an external
internal reference update sequence, during which
reference. At this point, the internal reference is
SYNC must be held low. To disable the internal
disconnected from the V
REF
pin (tri-state). Do not
reference, execute the write sequence illustrated in
attempt to drive the V
REF
pin externally and internally
Table 1 followed by at least two additional SCLK
at the same time indefinitely.
falling edges while SYNC is low.
Table 1. Write Sequence for Disabling the DAC8560 Internal Reference
DB23 DB0
0 1 0 0 1 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 1
Table 2. Enabling the DAC8560 Internal Reference (Write Sequence 1 of 2)
DB23 DB0
0 1 0 0 1 1 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0
Table 3. Enabling the DAC8560 Internal Reference (Write Sequence 2 of 2)
DB23 DB0
0 1 0 0 1 0 0 1 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 1
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