Datasheet

GND
DAC
Register
V
REF
V
OUT
50kW
62kW
50kW
REF(+)
RegisterString
REF( )-
V
FB
V
OUT
+
D
IN
65536
V
REF
V
REF
R
R
R
R
V
REF
2
R
DIVIDER
ToOutputAmplifier
(2xGain)
DAC8560
SLAS464B –DECEMBER 2006–REVISED NOVEMBER 2011 www.ti.com
THEORY OF OPERATION
DIGITAL-TO-ANALOG CONVERTER (DAC)
The DAC8560 architecture consists of a string DAC
followed by an output buffer amplifier. Figure 62
shows a block diagram of the DAC architecture.
Figure 62. DAC8560 Architecture
The input coding to the DAC8560 is straight binary,
so the ideal output voltage is given by:
(1)
where D
IN
= decimal equivalent of the binary code
that is loaded to the DAC register; it can range from 0
to 65535.
RESISTOR STRING
The resistor string section is shown in Figure 63. It is
simply a string of resistors, each of value R. The
code loaded into the DAC register determines at
which node on the string the voltage is tapped off to
be fed into the output amplifier by closing one of the
Figure 63. Resistor String
switches connecting the string to the amplifier. It is
monotonic because it is a string of resistors.
The inverting input of the output amplifier is available
OUTPUT AMPLIFIER
at the V
FB
pin. This feature allows better accuracy in
critical applications by tying the V
FB
point and the
The output buffer amplifier is capable of generating
amplifier output together directly at the load. Other
rail-to-rail voltages on its output, giving an output
signal conditioning circuitry may also be connected
range of 0V to V
DD
. It is capable of driving a load of
between these points for specific applications.
2kΩ in parallel with 1000pF to GND. The source and
sink capabilities of the output amplifier can be seen in
the Typical Characteristics. The slew rate is 1.8V/μs
with a full-scale settling time of 8μs with the output
unloaded.
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