Datasheet

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DAC8555 to 68HC11 Interface
MICROPROCESSOR INTERFACING
DAC8555 to 8051 Interface
68HC11
(1)
PC7
SCK
MOSI
SYNC
SCLK
D
IN
(1)Additionalpinsomittedforclarity.
DAC8555
80C51/80L51
(1)
P3.3
TXD
RXD
SYNC
SCLK
D
IN
(1)Additionalpinsomittedforclarity.
DAC8555
DAC8555 to TMS320 DSP Interface
DAC8555 to Microwire Interface
Microwire
TM
CS
SK
SO
SYNC
SCLK
D
IN
(1)Additionalpinsomittedforclarity.
DAC8555
MicrowireisaregisteredtrademarkofNationalSemiconductor.
DAC8555
TMS320DSP
SYNC
D
IN
SCLK
0.1 Fm 10 Fm
0.1 Fm 1mFto10mF
PositiveSupply
FSX
DX
CLKX
AV
DD
OutputA
OutputD
V D
OUT
V A
OUT
V H
REF
V L
REF
GND
Reference
Input
DAC8555
SLAS475B – NOVEMBER 2005 – REVISED OCTOBER 2006
Figure 52 shows a serial interface between the
DAC8555 and the 68HC11 microcontroller. SCK of
the 68HC11 drives the SCLK of the DAC8555, while
See Figure 50 for a serial interface between the
the MOSI output drives the serial data line of the
DAC8555 and a typical 8051-type microcontroller.
DAC. The SYNC signal is derived from a port line
The setup for the interface is as follows: TXD of the
(PC7), similar to the 8051 diagram.
8051 drives SCLK of the DAC8555, while RXD
drives the serial data line of the device. The SYNC
signal is derived from a bit-programmable pin on the
port of the 8051. In this case, port line P3.3 is used.
When data are to be transmitted to the DAC8555,
P3.3 is taken LOW. The 8051 transmits data in 8-bit
bytes; thus, only eight falling clock edges occur in
the transmit cycle. To load data to the DAC, P3.3 is
left LOW after the first eight bits are transmitted, then
a second and third write cycle are initiated to
Figure 52. DAC8555 to 68HC11 Interface
transmit the remaining data. P3.3 is taken HIGH
following the completion of the third write cycle. The
8051 outputs the serial data in a format that presents
The 68HC11 should be configured so that its CPOL
the LSB first, while the DAC8555 requires data with
bit is '0' and its CPHA bit is '1'. This configuration
the MSB as the first bit received. The 8051 transmit
causes data appearing on the MOSI output to be
routine must therefore take this into account, and
valid on the falling edge of SCLK. When data are
mirror the data as needed.
being transmitted to the DAC, the SYNC line is held
LOW (PC7). Serial data from the 68HC11 are
transmitted in 8-bit bytes with only eight falling clock
edges occurring in the transmit cycle. (Data are
transmitted MSB first.) In order to load data to the
DAC8555, PC7 is left LOW after the first eight bits
are transferred, then a second and third serial write
operation are performed to the DAC. PC7 is taken
HIGH at the end of this procedure.
Figure 50. DAC8555 to 80C51/80L51 Interface
Figure 53 shows the connections between the
DAC8555 and a TMS320 Digital Signal Processor
(DSP). A single DSP can control up to four
Figure 51 shows an interface between the DAC8555
DAC8555s without any interface logic.
and any Microwire-compatible device. Serial data are
shifted out on the falling edge of the serial clock and
is clocked into the DAC8555 on the rising edge of
the SK signal.
Figure 51. DAC8555 to Microwire Interface
Figure 53. DAC8555 to TMS320 DSP
22
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