Datasheet

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ABSOLUTE MAXIMUM RATINGS
(1)
ELECTRICAL CHARACTERISTICS
DAC8555
SLAS475B – NOVEMBER 2005 – REVISED OCTOBER 2006
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be
more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.
PACKAGING/ORDERING INFORMATION
(1)
MAXIMUM MAXIMUM
RELATIVE DIFFERENTIAL SPECIFIED
ACCURACY NONLINEARITY PACKAGE- PACKAGE TEMPERATURE PACKAGE ORDERING TRANSPORT
PRODUCT (LSB) (LSB) LEAD DESIGNATOR RANGE MARKING NUMBER MEDIA, QUANTITY
DAC8555IPW Tube, 90
DAC8555 ± 12 ± 1 TSSOP-16 PW –40 ° C to +105 ° C D8555
DAC8555IPWR Tape and Reel, 2000
(1) For the most current package and ordering information, see the Package Option Addendum at the end of this data sheet, or see the TI
web site at www.ti.com.
UNIT
AV
DD
, IOV
DD
to GND –0.3V to 6V
Digital input voltage to GND –0.3V to +AV
DD
+ 0.3V
V
O(A)
to V
O(D)
to GND –0.3V to +AV
DD
+ 0.3V
Operating temperature range –40 ° C to +105 ° C
Storage temperature range –65 ° C to +150 ° C
Junction temperature range (T
J
max) +150 ° C
Power dissipation (T
J
max – T
A
)/ θ
JA
θ
JA
Thermal impedance 118 ° C/W
θ
JC
Thermal impedance 29 ° C/W
(1) Stresses above those listed under absolute maximum ratings may cause permanent damage to the device. Exposure to absolute
maximum conditions for extended periods may affect device reliability.
V
DD
= 2.7V to 5.5V, all specifications –40 ° C to +105 ° C (unless otherwise noted).
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
STATIC PERFORMANCE
(1)
Resolution 16 Bits
Relative accuracy Measured by line passing through codes 485 and 64741 ± 4 ± 12 LSB
Differential nonlinearity 16-bit Monotonic ± 0.25 ± 1 LSB
Zero-scale error Measured by line passing through codes 485 and 64741 ± 2 ± 12 mV
Zero-scale error drift ± 5 µ V/ ° C
Full-scale error ± 0.3 ± 0.5 % of FSR
Measured by line passing through codes 485 and 64741,
(AV
DD
= 5V, V
REF
= 4.99V) and (AV
DD
= 2.7V, V
REF
= 2.69V)
Gain error ± 0.05 ± 0.15 % of FSR
ppm of
Gain temperature coefficient ± 1
FSR/ ° C
PSRR Power-Supply Rejection Ratio R
L
= 2k Ω , C
L
= 200pF 0.75 mV/V
OUTPUT CHARACTERISTICS
(2)
Output voltage range 0 V
REF
H V
To ± 0.003% FSR, 0200h to FD00h, R
L
= 2k Ω ,
8 10 µ s
0pF < C
L
< 200pF
Output voltage settling time
R
L
= 2k Ω , C
L
= 500pF 12 µ s
Slew rate 1.8 V/ µ s
R
L
= ∞ 470 pF
Capacitive load stability
R
L
= 2k Ω 1000 pF
(1) Linearity calculated using a reduced code range of 485 to 64741; output unloaded.
(2) Ensured by design and characterization; not production tested.
2
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