Datasheet

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POWER-DOWN MODES
V X
OUT
Amplifier
Resistor
String
DAC
Power-Down
Circuitry
Resistor
Network
DAC8555
SLAS475B – NOVEMBER 2005 – REVISED OCTOBER 2006
Individual channels can be separately powered
down, reducing the total power consumption. When
The DAC8555 uses four modes of operation. These
all channels are powered down, the DAC8555 power
modes are accessed by setting three bits (PD2, PD1,
consumption drops below 2 µ A. There is no power-up
and PD0) in the shift register and performing a Load
command. When a channel is updated with data, it
action to the DACs. The DAC8555 offers a very
automatically exits power-down. All channels exit
flexible power-down interface based on channel
power-down simultaneously after a broadcast data
register operation. A channel consists of a single
update. The time to exit power-down is
16-bit DAC with power-down circuitry, a temporary
approximately 5 µ s. See Table 1 and Table 2 for
storage register (TR), and a DAC register (DR). TR
power-down operation details.
and DR are both 18 bits wide. Two MSBs represent
a power-down condition and 16 LSBs represent data
for TR and DR. By adding bits 17 and 18 to TR and
DR, a power-down condition can be temporarily
stored and used as data. Internal circuits ensure that
DB15 and DB14 are transferred to TR17 and TR16
(DR17 and DR16), when DB16 = '1'.
The DAC8555 treats the power-down condition as
data; all the operational modes are still valid for
power-down. It is possible to broadcast a
power-down condition to all the DAC8555s in a
system, or it is possible to simultaneously
Figure 49. Output Stage During Power-Down
power-down a channel while updating data on other
(High-Impedance)
channels.
DB16, DB15, and DB14 = '100' (or '111') represent a
power-down condition with Hi-Z output impedance
for a selected channel. '101' represents a
power-down condition with 1k Ω output impedance
and '110' represents a power-down condition with
100k Ω output impedance.
18
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