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SYNC INTERRUPT POWER-ON RESET TO
24thFallingEdge24thFallingEdge
SCLK
SYNC
D
IN
1
DB22 DB0
DB1 DB0
InvalidWrite-SyncInterrupt:
SYNC HIGHBefore24thFallingEdge
ValidWrite-Buffer/DACUpdate:
SYNC HIGHAfter24thFallingEdge
2 1 2
DB23
DB22DB23
DAC8555
SLAS475B – NOVEMBER 2005 – REVISED OCTOBER 2006
ZERO-SCALE/MIDSCALE
In a normal write sequence, the SYNC line is kept
LOW for at least 24 falling edges of SCLK and the The DAC8555 contains a power-on reset circuit that
addressed DAC register is updated on the 24th controls the output voltage during power-up.
falling edge. However, if SYNC is brought HIGH Depending on RSTSEL signal, on power-up, the
before the 24th falling edge, it acts as an interrupt to DAC registers are reset and the output voltages are
the write sequence; the shift register is reset and the set to zero-scale (RSTSEL = 0) or midscale
write sequence is discarded. Neither an update of (RSTSEL = 1); they remain that way until a valid
the data buffer contents, DAC register contents, nor write sequence and load command are made to the
a change in the operating mode occurs (see respective DAC channel. The power-on reset is
Figure 48 ). useful in applications where it is important to know
the state of the output of each DAC while the device
is in the process of powering up.
Figure 48. Interrupt and Valid SYNC Timing
17
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