Datasheet

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ASYNCHRONOUS CLEAR
IOV
DD
AND VOLTAGE TRANSLATORS
INPUT SHIFT REGISTER
DAC8555
SLAS475B – NOVEMBER 2005 – REVISED OCTOBER 2006
After the 24th falling edge of SCLK is received, the
SYNC line may be kept LOW or brought HIGH. In
The DAC8555 output is asynchronously set to
either case, the minimum delay time from the 24th
zero-scale voltage or midscale voltage (depending
falling SCLK edge to the next falling SYNC edge
on RSTSEL) immediately after the RST pin is
must be met in order to properly begin the next
brought low. The RST signal resets all internal
cycle.
registers, and therefore, behaves like the Power-On
To assure the lowest power consumption of the
Reset. The RST pin must be brought back to high
device, care should be taken that the levels are as
before a write sequence is started.
close to each rail as possible. (Refer to the Typical
If the RSTSEL pin is high, RST signal going low
Characteristics section for Figure 41 , the Supply
resets all outputs to midscale. If the RSTSEL pin is
Current vs Logic Input Voltage transfer characteristic
low, RST signal going low resets all outputs to
curve.)
zero-scale. RSTSEL should be set at power up.
The IOV
DD
pin powers the the digital input structures
The input shift register (SR) of the DAC8555 is 24
of the DAC8555. For single-supply operation, it can
bits wide, as shown in Figure 47 , and is made up of
be tied to AV
DD
. For dual-supply operation, the
eight control bits (DB23–DB16) and 16 data bits
IOV
DD
pin provides interface flexibility with various
(DB15–DB0). DB23 and DB22 should always be '0'.
CMOS logic families and should be connected to the
logic supply of the system. Analog circuits and
LD1 (DB21) and LD0 (DB20) control the updating of
internal logic of the DAC8555 use AV
DD
as the
each analog output with the specified 16-bit data
supply voltage. The external logic high inputs get
value or power-down command. Bit DB19 is a don't
translated to AV
DD
by level shifters. These level
care bit that does not affect the operation of the
shifters use the IOV
DD
voltage as a reference to shift
DAC8555, and can be '1' or '0'. The DAC channel
the incoming logic HIGH levels to AV
DD
. IOV
DD
is
select bits (DB18, DB17) control the destination of
ensured to operate from 2.7V to 5.5V regardless of
the data (or power-down command) from DAC A
the AV
DD
voltage, which ensures compatibility with
through DAC D. The final control bit, PD0 (DB16),
various logic families. Although specified down to
selects the power-down mode of the DAC8555
2.7V, IOV
DD
will operate at as low as 1.8V with
channels.
degraded timing and temperature performance. For
lowest power consumption, logic V
IH
levels should be
as close as possible to IOV
DD
, and logic V
IL
levels
should be as close as possible to GND voltages.
DB23 DB12
0 0 LD1 LD0 X DAC Select 1 DAC Select 0 PD0 D15 D14 D13 D12
DB11 DB0
D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
Figure 47. DAC8555 Data Input Register Format
15
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