Datasheet

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THEORY OF OPERATION
DAC SECTION
DAC
Register
REF(+)
ResistorString
REF( )-
V L
REF
V H
REF
V
OUT
62kW
50kW 50kW
V
OUT
X + 2 V
REF
L )
ǒ
V
REF
H * V
REF
L
Ǔ
D
IN
65536
RESISTOR STRING
V
REF
H
V
REF
L
R
R
R
R
V
REF
2
R
DIVIDER
ToOutputAmplifier
(2xGain)
OUTPUT AMPLIFIER
SERIAL INTERFACE
DAC8555
SLAS475B – NOVEMBER 2005 – REVISED OCTOBER 2006
The architecture of each channel of the DAC8555
consists of a resistor-string DAC followed by an
output buffer amplifier. Figure 45 shows a simplified
block diagram of the DAC architecture.
Figure 45. DAC8555 Architecture
The input coding for each device can be 2's
complement or unipolar straight binary, so the ideal
output voltage is given by:
where D
IN
= decimal equivalent of the binary code
that is loaded to the DAC register; it can range from
0 to 65535.
The resistor string section is shown in Figure 46 . It is
Figure 46. Resistor String
simply a divide-by-2 resistor followed by a string of
resistors. The code loaded into the DAC register
determines at which node on the string the voltage is
The write sequence begins by bringing the SYNC
tapped off. This voltage is then applied to the output
line LOW. Data from the D
IN
line are clocked into the
amplifier by closing one of the switches connecting
24-bit shift register on each falling edge of SCLK.
the string to the amplifier.
The serial clock frequency can be as high as 50MHz,
making the DAC8555 compatible with high-speed
DSPs. On the 24th falling edge of the serial clock,
the last data bit is clocked into the shift register and
Each output buffer amplifier is capable of generating
the shift register gets locked. Further clocking does
rail-to-rail voltages on its output that approaches an
not change the shift register data. Once 24 bits are
output range of 0V to AV
DD
(gain and offset errors
locked into the shift register, the eight MSBs are
must be taken into account). Each buffer is capable
used as control bits and the 16 LSBs are used as
of driving a load of 2k Ω in parallel with 1000pF to
data. After receiving the 24th falling clock edge, the
GND. The source and sink capabilities of the output
DAC8555 decodes the eight control bits and 16 data
amplifier can be seen in the Typical Characteristics .
bits to perform the required function, without waiting
for a SYNC rising edge. A new SPI sequence starts
at the next falling edge of SYNC. A rising edge of
SYNC before the 24-bit sequence is complete resets
The DAC8555 uses a 3-wire serial interface ( SYNC,
the SPI interface; no data transfer occurs.
SCLK, and D
IN
), which is compatible with SPI,
QSPI™, and Microwire™ interface standards, as well
as most DSPs. See the Serial Write Operation timing
diagram for an example of a typical write sequence.
14
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