Datasheet

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PIN CONFIGURATION
V A
OUT
LDAC
ENABLE
A1
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
DAC8554
V B
OUT
V H
REF
AV
DD
V L
REF
GND
V C
OUT
V D
OUT
A0
IOV
DD
D
IN
SCLK
SYNC
DAC8554
SLAS431B – JUNE 2005 – REVISED OCTOBER 2006
PIN DESCRIPTIONS
PIN NAME DESCRIPTION
1 V
OUT
A Analog output voltage from DAC A.
2 V
OUT
B Analog output voltage from DAC B.
3 V
ref
H Positive reference voltage input.
4 AV
DD
Power supply input, 2.7V to 5.5V.
5 V
ref
L Negative reference voltage input.
6 GND Ground reference point for all circuitry on the part.
7 V
OUT
C Analog output voltage DAC C.
8 V
OUT
D Analog output voltage DAC D.
Level-triggered control input (active LOW). This is the frame synchronization signal for the input data. When
SYNC goes LOW, it enables the input shift register and data is transferred in on the falling edges of the
9 SYNC following clocks. The DAC is updated following the 24th clock (unless SYNC is taken HIGH before this edge,
in which case the rising edge of SYNC acts as an interrupt and the write sequence is ignored by the
DAC8554). Schmitt-Trigger-Logic input.
10 SCLK Serial clock input. Data can be transferred at rates up to 50MHz. Schmitt-Trigger-Logic input.
Serial data input. Data is clocked into the 24-bit input shift register on each falling edge of the serial clock
11 D
IN
input. Schmitt-Trigger-Logic input.
12 IOV
DD
Digital input-output power supply
13 A0 Address 0 — sets device address; see Table 2
14 A1 Address 1 — sets device address; see Table 2
15 ENABLE Active LOW, ENABLE LOW connects the SPI interface to the serial port.
16 LDAC Load DACs, rising edge triggered, loads all DAC registers.
4
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