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SYNC INTERRUPT POWER-ON RESET
24thFallingEdge24thFallingEdge
SCLK
SYNC
D
IN
1
DB22 DB0
DB1 DB0
InvalidWrite-SyncInterrupt:
SYNC HIGHBefore24thFallingEdge
ValidWrite-Buffer/DACUpdate:
SYNC HIGHAfter24thFallingEdge
2 1 2
DB23
DB22DB23
DAC8554
SLAS431B – JUNE 2005 – REVISED OCTOBER 2006
In a normal write sequence, the SYNC line is kept The DAC8554 contains a power-on reset circuit that
LOW for at least 24 falling edges of SCLK and the controls the output voltage during power-up. On
addressed DAC register is updated on the 24th power-up, the DAC registers are filled with zeros and
falling edge. However, if SYNC is brought HIGH the output voltages are set to zero-scale; they
before the 24th falling edge, it acts as an interrupt to remain that way until a valid write sequence and load
the write sequence; the shift register is reset and the command are made to the respective DAC channel.
write sequence is discarded. Neither an update of The power-on reset is useful in applications where it
the data buffer contents, DAC register contents, nor is important to know the state of the output of each
a change in the operating mode occurs (see DAC while the device is in the process of powering
Figure 48 ). up. No device pin should be brought high before
power is applied to the device.
Figure 48. Interrupt and Valid SYNC Timing
17
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