Datasheet

www.ti.com
INPUT SHIFT REGISTER
IOV
DD
AND VOLTAGE TRANSLATORS
DAC8554
SLAS431B – JUNE 2005 – REVISED OCTOBER 2006
After the 24th falling edge of SCLK is received, the
SYNC line may be kept LOW or brought HIGH. In
The input shift register (SR) of the DAC8554 is 24
either case, the minimum delay time from the 24th
bits wide, as shown in Figure 47 , and is made up of
falling SCLK edge to the next falling SYNC edge
eight control bits (DB23–DB16) and 16 data bits
must be met in order to properly begin the next
(DB15–DB0). The first two control bits (DB23 and
cycle.
DB22) are the address match bits. The DAC8554
To assure the lowest power consumption of the
offers additional hardware-enabled addressing
device, care should be taken that the levels are as
capability, allowing a single host to talk to up to four
close to each rail as possible. [Refer to the Typical
DAC8554s through a single SPI bus without any glue
Characteristics section for the Supply Current vs
logic, enabling up to 16-channel operation. The state
Logic Input Voltage (5V and 2.7V ) transfer
of DB23 should match the state of pin A1; similarly,
characteristic curves.]
the state of DB22 should match the state of pin A0. If
there is no match, the control command and the data
(DB21...DB0) are ignored by the DAC8554. That is, if
there is no match, the DAC8554 is not addressed.
The IOV
DD
pin powers the digital input structures of
Address matching can be overridden by the
the DAC8554. For single-supply operation, it can be
broadcast update.
tied to AV
DD
. For dual-supply operation, the IOV
DD
pin provides interface flexibility with various CMOS
LD1 (DB21) and LD0 (DB20) control the updating of
logic families and should be connected to the logic
each analog output with the specified 16-bit data
supply of the system. Analog circuits and internal
value or power-down command. Bit DB19 is a don't
logic of the DAC8554 use AV
DD
as the supply
care bit that does not affect the operation of the
voltage. The external logic high inputs get translated
DAC8554, and can be '1' or '0'. The DAC channel
to AV
DD
by level shifters. These level shifters use the
select bits (DB18, DB17) control the destination of
IOV
DD
voltage as a reference to shift the incoming
the data (or power-down command) from DAC A
logic HIGH levels to AV
DD
. IOV
DD
is ensured to
through DAC D. The final control bit, PD0 (DB16),
operate from 2.7V to 5.5V regardless of the AV
DD
selects the power-down mode of the DAC8554
voltage, which ensures compatibility with various
channels.
logic families. Although specified down to 2.7V,
IOV
DD
will operate at as low as 1.8V with degraded
timing and temperature performance. For lowest
power consumption, logic V
IH
levels should be as
close as possible to IOV
DD
, and logic V
IL
levels
should be as close as possible to GND voltages
DB23 DB12
A1 A0 LD1 LD0 X DAC Select 1 DAC Select 0 PD0 D15 D14 D13 D12
DB11 DB0
D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
Figure 47. DAC8554 Data Input Register Format
15
Submit Documentation Feedback