Datasheet

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PIN CONFIGURATION
1
2
3
4
DAC8552
8
7
6
5
V
V
V
V
B
A
DD
REF
OUT
OUT
GND
D
SCLK
SYNC
IN
DAC8552
SLAS430A – JULY 2006 – REVISED OCTOBER 2006
DGK PACKAGE
MSOP-8
(Top View)
PIN DESCRIPTIONS
PIN NAME FUNCTION
1 V
DD
Power supply input, 2.7V to 5.5V
2 V
REF
Reference voltage input
3 V
OUT
B Analog output voltage from DAC B
4 V
OUT
A Analog output voltage from DAC A
Level triggered SYNC input (active LOW). This is the frame synchronization signal for the input data. When SYNC goes
LOW, it enables the input shift register and data is transferred on the falling edges of SCLK. The action specified by the
5 SYNC 8-bit control byte and 16-bit data word is executed following the 24th falling SCLK clock edge (unless SYNC is taken
HIGH before this edge, in which case the rising edge of SYNC acts as an interrupt and the write sequence is ignored
by the DAC8552). Schmitt-Trigger logic input.
6 SCLK Serial Clock Input. Data can be transferred at rates up to 30MHz at 5V. Schmitt-Trigger logic input.
Serial Data Input. Data is clocked into the 24-bit input shift register on the falling edge of the serial clock input.
7 D
IN
Schmitt-Trigger logic input.
8 GND Ground reference point for all circuitry on the part.
4
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