Datasheet

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APPLICATION INFORMATION
CURRENT CONSUMPTION
OUTPUT VOLTAGE STABILITY
DRIVING RESISTIVE AND CAPACITIVE
SETTLING TIME AND OUTPUT GLITCH
CROSSTALK AND AC PERFORMANCE
DIFFERENTIAL AND INTEGRAL
DAC8552
SLAS430A – JULY 2006 – REVISED OCTOBER 2006
In addition, the DAC8552 can achieve typical ac
performance of 96dB signal-to-noise ratio (SNR) and
–85dB total harmonic distortion (THD), making the
The DAC8552 typically consumes 170 µ A at V
DD
=
DAC8552 a solid choice for applications requiring
5 V and 155 µ A at V
DD
= 2.7V for each active
high SNR at output frequencies at or below 10kHz.
channel, excluding reference current consumption.
Additional current consumption can occur at the
digital inputs if V
IH
<< V
DD
. For most efficient power
operation, CMOS logic levels are recommended at
The DAC8552 exhibits excellent temperature stability
the digital input to the DAC.
of 5ppm/ ° C typical output voltage drift over the
In power-down mode, typical current consumption is specified temperature range of the device. This
700nA. A delay time of 10ms to 20ms after a stability enables the output voltage of each channel
power-down command is issued to the DAC is to stay within a ± 25 µ V window for a ± 1 ° C ambient
typically sufficient for the power-down current to drop temperature change.
below 10 µ A.
Good power-supply rejection ratio (PSRR)
performance reduces supply noise present on V
DD
from appearing at the outputs. Combined with good
LOADS
dc noise performance and true 16-bit differential
linearity, the DAC8552 becomes an ideal choice for
The DAC8552 output stage is capable of driving
closed-loop control applications.
loads of up to 1000pF while remaining stable. Within
the offset and gain error margins, the DAC8552 can
operate rail-to-rail when driving a capacitive load.
Resistive loads of 2k Ω can be driven by the PERFORMANCE
DAC8552 while achieving good load regulation.
The DAC8552 settles to ± 0.003% of its full-scale
When the outputs of the DAC are driven to the
range within 10 µ s, driving a 200pF, 2k Ω load. For
positive rail under resistive loading, the PMOS
good settling performance, the outputs should not
transistor of each Class-AB output stage can enter
approach the top and bottom rails. Small signal
into the linear region. When this scenario occurs, the
settling time is under 1 µ s, enabling data update rates
added IR voltage drop deteriorates the linearity
exceeding 1MSPS for small code changes.
performance of the DAC. This deterioration only
occurs within approximately the top 100mV of the
Many applications are sensitive to undesired
DACs output voltage characteristic. Under resistive
transient signals such as glitch. The DAC8552 has a
loading conditions, good linearity is preserved as
proprietary, ultra-low glitch architecture addressing
long as the output voltage is at least 100mV below
such applications. Code-to-code glitches rarely
the V
DD
voltage.
exceed 1mV and they last under 0.3 µ s. Typical glitch
energy is an outstanding 0.15nV-s. Theoretical
worst-case glitch should occur during a 256LSB step,
but it is so low, it cannot be detected.
The DAC8552 architecture uses separate resistor
strings for each DAC channel in order to achieve
ultra-low crosstalk performance. dc crosstalk seen at
NONLINEARITY
one channel during a full-scale change on the
neighboring channel is typically less than 0.5 LSBs.
The DAC8552 uses precision, thin-film resistors to
The ac crosstalk measured (for a full-scale, 1kHz
achieve monotonicity and good linearity. Typical
sine wave output generated at one channel, and
linearity error is ± 4LSBs, with a ± 0.3mV error for a
measured at the remaining output channel) is
5V range. Differential linearity is typically ± 0.35LSBs,
typically under –100dB.
with a ± 27 µ V error for a consecutive code change.
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