Datasheet

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MICROPROCESSOR INTERFACING
DAC8552 to 8051 INTERFACE DAC8552 to 68HC11 INTERFACE
68HC11
(1)
PC7
SCK
MOSI
SYNC
SCLK
D
IN
NOTE:(1)Additionalpinsomittedforclarity.
DAC8552
(1)
80C51/80L51
(1)
P3.3
TXD
RXD
SYNC
SCLK
D
IN
NOTE:(1)Additionalpinsomittedforclarity.
DAC8552
(1)
DAC8552 to TMS320 DSP INTERFACE
DAC8552 to Microwire INTERFACE
Microwire
TM
CS
SK
SO
SYNC
SCLK
D
IN
NOTE:(1)Additionalpinsomittedforclarity.
DAC8552
(1)
DAC8552
TMS320DSP
SYNC
D
IN
SCLK
0.1 Fm 10 Fm
0.1 Fm 1mFto10mF
PositiveSupply
FSX
DX
CLKX
V
DD
OutputA
OutputB
V B
OUT
V A
OUT
V
REF
GND
Reference
Input
DAC8552
SLAS430A – JULY 2006 – REVISED OCTOBER 2006
Figure 46 shows a serial interface between the Figure 48 shows a serial interface between the
DAC8552 and a typical 8051-type microcontroller. DAC8552 and the 68HC11 microcontroller. SCK of
The setup for the interface is as follows: TXD of the the 68HC11 drives the SCLK of the DAC8552, while
8051 drives SCLK of the DAC8552, while RXD the MOSI output drives the serial data line of the
drives the serial data line of the device. The SYNC DAC. The SYNC signal is derived from a port line
signal is derived from a bit-programmable pin on the (PC7), similar to the 8051 diagram.
port of the 8051. In this case, port line P3.3 is used.
When data are to be transmitted to the DAC8552,
P3.3 is taken LOW. The 8051 transmits data in 8-bit
bytes; thus, only eight falling clock edges occur in
the transmit cycle. To load data to the DAC, P3.3 is
left LOW after the first eight bits are transmitted, then
a second and third write cycle are initiated to
transmit the remaining data. P3.3 is taken HIGH
following the completion of the third write cycle. The
Figure 48. DAC8552 to 68HC11 Interface
8051 outputs the serial data in a format that presents
the LSB first, while the DAC8552 requires its data
with the MSB as the first bit received. The 8051
The 68HC11 should be configured so that its CPOL
transmit routine must therefore take this into account,
bit is '0' and its CPHA bit is '1'. This configuration
and mirror the data as needed
causes data appearing on the MOSI output to be
valid on the falling edge of SCK. When data are
being transmitted to the DAC, the SYNC line is held
LOW (PC7). Serial data from the 68HC11 are
transmitted in 8-bit bytes with only eight falling clock
edges occurring in the transmit cycle. (Data are
transmitted MSB first.) In order to load data to the
DAC8552, PC7 is left LOW after the first eight bits
are transferred, then a second and third serial write
operation are performed to the DAC. PC7 is taken
Figure 46. DAC8552 to 80C51/80L51 Interface
HIGH at the end of this procedure.
Figure 49 shows the connections between the
Figure 47 shows an interface between the DAC8552
DAC8552 and a TMS320 digital signal processor. By
and any Microwire-compatible device. Serial data are
decoding the FSX signal, multiple DAC8552s can be
shifted out on the falling edge of the serial clock and
connected to a single serial port of the DSP.
clocked into the DAC8552 on the rising edge of the
SK signal.
Figure 47. DAC8552 to Microwire Interface
Figure 49. DAC8552 to TMS320 DSP
17
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