Datasheet

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SYNC INTERRUPT
POWER-ON RESET
POWER-DOWN MODES
V A,B
OUT
Amplifier
Resistor
String
DAC
Power-Down
Circuitry
Resistor
Network
24thFallingEdge24thFallingEdge
SCLK
SYNC
D
IN
1
DB22 DB0
DB1 DB0
InvalidWrite-SyncInterrupt:
SYNC HIGHBefore24thFallingEdge
ValidWrite-Buffer/DACUpdate:
SYNC HIGHAfter24thFallingEdge
2 1 2
DB23
DB22DB23
DAC8552
SLAS430A – JULY 2006 – REVISED OCTOBER 2006
3V). Not only does the supply current fall, but the
output stage is also internally switched from the
In a normal write sequence, the SYNC line is kept
output of the amplifier to a resistor network of known
LOW for at least 24 falling edges of SCLK and the
values. This configuration has the advantage that the
addressed DAC register is updated on the 24th
output impedance of the device is known while it is in
falling edge. However, if SYNC is brought HIGH
power-down mode. There are three different options
before the 24th falling edge, it acts as an interrupt to
for power-down: The output is connected internally to
the write sequence; the shift register is reset and the
GND through a 1k Ω resistor, a 100k Ω resistor, or it is
write sequence is discarded. Neither an update of
left open-circuited (High-Impedance). The output
the data buffer contents, DAC register contents nor a
stage is illustrated in Figure 44 .
change in the operating mode occurs, as shown in
Figure 45 .
Table 3. Operating Modes
PD1 (DB17) PD0 (DB16) OPERATING MODE
0 0 Normal Operation
The DAC8552 contains a power-on reset circuit that
— — Power-down modes
controls the output voltage during power-up. Upon
0 1 Output typically 1k Ω to GND
power-up, the DAC registers are filled with zeros and
the output voltages are set to zero-scale; they
1 0 Output typically 100k Ω to GND
remain that way until a valid write sequence and load
1 1 High impedance
command are made to the respective DAC channel.
The power-on reset is useful in applications where it
is important to know the state of the output of each
DAC output while the device is in the process of
powering up.
No device pin should be brought high before power
is applied to the device.
The DAC8552 usees four modes of operation. These
modes are accessed by setting two bits (PD1 and
Figure 44. Output Stage During Power-Down
PD0) in the control register to one or both DACs.
(High Impedance)
Table 3 shows how the state of the bits correspond
to the register and perform a mode of operation on
each channel of the device. (Each DAC channel can
All analog circuitry is shut down when the
be powered down simultaneously or independently of
power-down mode is activated. Each DAC will exit
each other. Power-down occurs after proper data is
power-down when PD0 and PD1 are set to '0', new
written into PD0 and PD1 and a Load command
data is written to the Data Buffer, and the DAC
occurs.) See the Operation Examples section for
channel receives a Load command. The time to exit
additional information.
power-down is typically 2.5 µ s for V
DD
= 5V and 5 µ s
for V
DD
= 3V (see the Typical Characteristics ).
When both bits are set to '0', the device works
normally with a typical power consumption of 450 µ A
at 5V. For the three power-down modes, however,
the supply current falls to 700nA at 5V (400nA at
Figure 45. Interrupt and Valid SYNC Timing
15
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