Datasheet

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INPUT SHIFT REGISTER
DAC8552
SLAS430A – JULY 2006 – REVISED OCTOBER 2006
cycle. To assure the lowest power consumption of the destination of the data (or power-down
the device, care should be taken that the levels are command) between DAC A and DAC B. The final
as close to each rail as possible. (See the Typical two control bits, PD0 (DB16) and PD1 (DB17), select
Characteristics section for the Supply Current vs the power-down mode of one or both of the DAC
Logic Input Voltage transfer characteristic curve). channels. The four modes are normal mode or any
one of three power-down modes. A more complete
description of the operational modes of the DAC8552
can be found in the Power-Down Modes section. The
The input shift register of the DAC8552 is 24 bits
remaining 16 bits of the 24-bit input word make up
wide (shown in Figure 43 ) and is made up of eight
the data bits. These bits are transferred to the
control bits (DB16–DB23) and 16 data bits
specified Data Buffer or DAC Register, depending on
(DB0–DB15). The first two control bits (DB22 and
the command issued by the control byte, on the 24th
DB23) are reserved and must be '0' for proper
falling edge of SCLK. See Table 1 and Table 2 for
operation. LDA (DB20) and LD B (DB21) control the
more information.
updating of each analog output with the specified
16-bit data value or power- down command. Bit
DB19 is a don't care bit that does not affect the
operation of the DAC8552, and can be '1' or '0'. The
following control bit, Buffer Select (DB18), controls
DB23 DB12
0 0 LDB LDA X Buffer Select PD1 PD0 D15 D14 D13 D12
DB11 DB0
D11 D10 D9 D8 D7 D6 D5 D5 D3 D2 D1 D0
Figure 43. DAC8552 Data Input Register Format
Table 1. Control Matrix
D23 D22 D21 D20 D19 D18 D17 D16 D15 D14 D13–D0
Don't Buffer MSB-2...
Reserved Reserved Load B Load A Care Select PD1 PD0 MSB MSB-1 LSB
0 = A,
(Always Write 0) 1 = B DESCRIPTION
0 0 0 0 X # 0 0 Data WR Buffer # w/Data
0 0 0 0 X # See Table 2 X WR Buffer # w/Power-down Command
0 0 0 1 X # 0 0 Data WR Buffer # w/Data and Load DAC A
WR Buffer A w/Power-Down Command and LOAD DAC A
0 0 0 1 X 0 See Table 2 X
(DAC A Powered Down)
0 0 0 1 X 1 See Table 2 X WR Buffer B w/Power-Down Command and LOAD DAC A
0 0 1 0 X # 0 0 Data WR Buffer # w/Data and Load DAC B
0 0 1 0 X 0 See Table 2 X WR Buffer A w/Power-Down Command and LOAD DAC B
WR Buffer B w/Power-Down Command and LOAD DAC B
0 0 1 0 X 1 See Table 2 X
(DAC B Powered Down)
0 0 1 1 X # 0 0 Data WR Buffer # w/Data and Load DACs A and B
WR Buffer A w/Power-Down Command and Load DACs A and
0 0 1 1 X 0 See Table 2 X
B (DAC A Powered Down)
WR Buffer B w/Power-Down Command and Load DACs A and
0 0 1 1 X 1 See Table 2 X
B (DAC B Powered Down)
Table 2. Power-Down Commands
D17 D16
PD1 PD0 OUTPUT IMPEDANCE POWER DOWN COMMANDS
0 1 1k Ω
1 0 100k Ω
1 1 High Impedance
14
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