Datasheet

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THEORY OF OPERATION
DAC SECTION
DAC
Register
REF(+)
ResistorString
REF( )-
GND
V
REF
V
OUT
62kW
50kW 50kW
V
OUT
A, B + V
REF
D
65536
(1)
V
REF
R
R
R
R
V
REF
2
R
DIVIDER
ToOutputAmplifier
(2xGain)
RESISTOR STRING
OUTPUT AMPLIFIER
SERIAL INTERFACE
DAC8552
SLAS430A – JULY 2006 – REVISED OCTOBER 2006
The architecture of each channel of the DAC8552
consists of a resistor-string DAC followed by an
output buffer amplifier. Figure 41 shows a simplified
block diagram of the DAC architecture.
Figure 41. DAC8552 Architecture
The input coding for each device is unipolar straight
binary, so the ideal output voltage is given by:
Where:
D = decimal equivalent of the binary code that is
loaded to the DAC register; it can range from 0
to 65535.
V
OUT
A,B refers to channel A or B.
Figure 42. Resistor String
The resistor string section is shown in Figure 42 . It is
simply a divide-by-2 resistor followed by a string of
The write sequence begins by bringing the SYNC
resistors, each of value R. The code loaded into the
line LOW. Data from the D
IN
line are clocked into the
DAC register determines at which node on the string
24-bit shift register on each falling edge of SCLK.
the voltage is tapped off. This voltage is then applied
The serial clock frequency can be as high as 30MHz,
to the output amplifier by closing one of the switches
making the DAC8552 compatible with high speed
connecting the string to the amplifier.
DSPs. On the 24th falling edge of the serial clock,
the last data bit is clocked into the shift register and
the shift register is locked. Further clocking does not
change the shift register data. Once 24 bits are
Each output buffer amplifier is capable of generating
locked into the shift register, the eight MSBs are
rail-to-rail voltages on its output which approaches
used as control bits and the 16 LSBs are used as
an output range of 0V to V
DD
(gain and offset errors
data. After receiving the 24th falling clock edge, the
must be taken into account). Each buffer is capable
DAC8552 decodes the eight control bits and 16 data
of driving a load of 2k Ω in parallel with 1000pF to
bits to perform the required function, without waiting
GND. The source and sink capabilities of the output
for a SYNC rising edge. A new SPI sequence starts
amplifier can be seen in the Typical Characteristics.
at the next falling edge of SYNC. A rising edge of
SYNC before the 24-bit sequence is complete resets
the SPI interface; no data transfer occurs.
The DAC8552 uses a 3-wire serial interface ( SYNC,
After the 24th falling edge of SCLK is received, the
SCLK, and D
IN
) that is compatible with SPI™,
SYNC line may be kept LOW or brought HIGH. In
QSP™, and Microwire™ interface standards, as well
either case, the minimum delay time from the 24th
as most DSPs. See the Serial Write Operation
falling SCLK edge to the next falling SYNC edge
Timing Diagram for an example of a typical write
must be met in order to properly begin the next
sequence.
13
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