Datasheet

www.ti.com
PIN CONFIGURATION
1
2
3
4
DAC8551
8
7
6
5
V
V
V
V
DD
REF
FB
OUT
GND
D
SCLK
SYNC
IN
DAC8551
SLAS429B – APRIL 2005 – REVISED OCTOBER 2006
DGK PACKAGE
MSOP-8
(Top View)
PIN DESCRIPTIONS
PIN NAME DESCRIPTION
1 V
DD
Power supply input, 2.7V to 5.5V.
2 V
REF
Reference voltage input.
3 V
FB
Feedback connection for the output amplifier. For voltage output operation, tie to V
OUT
externally.
4 V
OUT
Analog output voltage from DAC. The output amplifier has rail-to-rail operation.
Level-triggered control input (active LOW). This is the frame synchronization signal for the input data. When SYNC goes
LOW, it enables the input shift register and data is transferred in on the falling edges of the following clocks. The DAC is
5 SYNC
updated following the 24th clock (unless SYNC is taken HIGH before this edge, in which case the rising edge of SYNC
acts as an interrupt and the write sequence is ignored by the DAC8551). Schmitt-Trigger logic input.
6 SCLK Serial clock input. Data can be transferred at rates up to 30MHz. Schmitt-Trigger logic input.
Serial data input. Data is clocked into the 24-bit input shift register on each falling edge of the serial clock input.
7 D
IN
Schmitt-Trigger logic input.
8 GND Ground reference point for all circuitry on the part.
4
Submit Documentation Feedback