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SYNC INTERRUPT
INPUT SHIFT REGISTER
POWER-ON RESET
CLK
SYNC
D
IN
ValidWriteSequence:OutputUpdates
onthe24thFallingEdge
24thFallingEdge 24thFallingEdge
DB23 DB80 DB23 DB80
DAC8551
SLAS429B APRIL 2005 REVISED OCTOBER 2006
At this point, the SYNC line may be kept LOW or
brought HIGH. In either case, it must be brought
In a normal write sequence, the SYNC line is kept
HIGH for a minimum of 33ns before the next write
LOW for at least 24 falling edges of SCLK and the
sequence so that a falling edge of SYNC can initiate
DAC is updated on the 24th falling edge. However, if
the next write sequence. As previously mentioned, it
SYNC is brought HIGH before the 24th falling edge,
must be brought HIGH again just before the next
it acts as an interrupt to the write sequence. The shift
write sequence.
register is reset, and the write sequence is seen as
invalid. Neither an update of the DAC register
contents nor a change in the operating mode occurs,
as shown in Figure 48 .
The input shift register is 24 bits wide, as shown in
Figure 47 . The first six bits are don't care bits. The
next two bits (PD1 andPD0) are control bits that
control which mode of operation the part is in
The DAC8551 contains a power-on-reset circuit that
(normal mode or any one of three power-down
controls the output voltage during power up. On
modes). A more complete description of the various
power up, the DAC registers are filled with zeros and
modes is located in the Power-Down Modes section.
the output voltages are 0V; they remain that way
The next 16 bits are the data bits. These bits are
until a valid write sequence is made to the DAC. The
transferred to the DAC register on the 24th falling
power-on reset is useful in applications where it is
edge of SCLK.
important to know the state of the output of the DAC
while it is in the process of powering up.
DB23 DB0
X X X X X X PD1 PD0 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
Figure 47. DAC8551 Data Input Register Format
Figure 48. SYNC Interrupt Facility
16
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