Datasheet

www.ti.com
2
3.2 Host Processor Interface
3.3 EVM Stacking
EVM Operation
Figure 11. DAC8552 EVM Default Jumper Configuration
The host processor basically drives the DAC; therefore, the proper operation of the DAC depends on the
successful configuration between the host processor and the EVM board. Additionally, a properly written
code is required to operate the DAC.
A custom cable can be made specific to the host interface platform. The EVM allows an interface to the
host processor through the J2 header connector for the serial control signals and the serial data input. The
output can be monitored through the J4 header connector.
An interface adapter board also is available for a specific TI DSP starter kit as well as an MSP430-based
microprocessor as mentioned in Section 1. Using the TI Interface Board alleviates the task of building
customized cables and allows easy configuration of a simple evaluation system.
The DAC8550/51/52 interfaces with any host processor capable of handling SPI™ protocols or the TI
DSP. For more information regarding the DAC8550/51/52 data interface, see the data sheet.
The stacking of EVMs is possible if users need to evaluate two DAC8550/51/52 devices to yield a total of
up to two-channel (for DAC8550/51) or four-channel (for DAC8552) outputs. A maximum of two EVMs are
allowed because the output terminal, J4, dictates the number of DAC channels that can be connected
without output bus contention. Table 4 shows how the DAC output channels are mapped into the output
terminal, J4, with respect to the jumper position of W2 and W7.
Table 4. DAC Output Channel Mapping
Reference Jumper Position Function
W2 1-2 DAC output A (V
OUT
A) is routed to J4-2.
2-3 DAC output A (V
OUT
A) is routed to J4-6.
W7 1-2 DAC output B (V
OUT
B) is routed to J4-10.
2-3 DAC output B (V
OUT
B) is routed to J4-14.
In order to allow exclusive control of each EVM that is stacked together, each DAC8550/51/52 must have
a separate SYNC signal. This is accomplished in hardware by routing the SYNC signal of the first EVM
through CS (P2/J2 pin 1) by shorting pins 1-2 of jumper W6. The second EVM should use the FSX signal
(P2/J2 pin 7) to drive the SYNC signal by shorting pins 2-3 of the jumper W6. The output can be mapped
as described in Table 4 for each of the EVMs stacked.
DAC8550/51/52 Evaluation Module12 SLAU172A – December 2005 – Revised September 2006
Submit Documentation Feedback