Datasheet
Microwire
TM
CS
SK
SO
SYNC
SCLK
D
IN
NOTE:(1)Additionalpinsomittedforclarity.
DAC8550
(1)
68HC11
(1)
PC7
SCK
MOSI
SYNC
SCLK
D
IN
NOTE:(1)Additionalpinsomittedforclarity.
DAC8550
(1)
80C51/80L51
(1)
P3.3
TXD
RXD
SYNC
SCLK
D
IN
NOTE:(1)Additionalpinsomittedforclarity.
DAC8550
(1)
DAC8550
SLAS476E –MARCH 2006–REVISED MARCH 2012
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MICROPROCESSOR INTERFACING
DAC8550 to 8051 Interface
See Figure 50 for a serial interface between the
DAC8550 and a typical 8051-type microcontroller.
The setup for the interface is as follows: TXD of the
8051 drives SCLK of the DAC8550, while RXD drives
the serial data line of the device. The SYNC signal is
Figure 51. DAC8550 to Microwire Interface
derived from a bit-programmable pin on the port of
the 8051. In this case, port line P3.3 is used. When
data are to be transmitted to the DAC8550, P3.3 is
DAC8550 to 68HC11 Interface
taken LOW. The 8051 transmits data in 8-bit bytes;
Figure 52 shows a serial interface between the
thus, only eight falling clock edges occur in the
DAC8550 and the 68HC11 microcontroller. SCK of
transmit cycle. To load data to the DAC, P3.3 is left
the 68HC11 drives the SCLK of the DAC8550, while
LOW after the first eight bits are transmitted, then a
the MOSI output drives the serial data line of the
second write cycle is initiated to transmit the second
DAC. The SYNC signal is derived from a port line
byte of data. P3.3 is taken HIGH following the
(PC7), similar to the 8051 diagram.
completion of the third write cycle. The 8051 outputs
the serial data in a format that has the LSB first. The
DAC8550 requires its data with the MSB as the first
bit received. The 8051 transmit routine must therefore
take this into account, and mirror the data as needed.
Figure 52. DAC8550 to 68HC11 Interface
The 68HC11 should be configured so that its CPOL
bit is '0' and its CPHA bit is '1'. This configuration
Figure 50. DAC8550 to 80C51/80L51 Interface
causes data appearing on the MOSI output to be
valid on the falling edge of SCK. When data are
being transmitted to the DAC, the SYNC line is held
DAC8550 to Microwire Interface
LOW (PC7). Serial data from the 68HC11 are
Figure 51 shows an interface between the DAC8550
transmitted in 8-bit bytes with only eight falling clock
and any Microwire-compatible device. Serial data are
edges occurring in the transmit cycle. (Data are
shifted out on the falling edge of the serial clock and
transmitted MSB first.) In order to load data to the
clocked into the DAC8550 on the rising edge of the
DAC8550, PC7 is left LOW after the first eight bits
SK signal.
are transferred, then a second and third serial write
operation are performed to the DAC. PC7 is taken
HIGH at the end of this procedure.
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