Datasheet

CLK
SYNC
D
IN
ValidWriteSequence:OutputUpdates
onthe24thFallingEdge
24thFallingEdge 24thFallingEdge
DB23 DB80 DB23 DB80
DAC8550
SLAS476E –MARCH 2006–REVISED MARCH 2012 www.ti.com
than it does when it is LOW, SYNC should be idled SYNC INTERRUPT
LOW between write sequences for lowest power
In a normal write sequence, the SYNC line is kept
operation of the part. As mentioned above, it must be
LOW for at least 24 falling edges of SCLK and the
brought HIGH again just before the next write
DAC is updated on the 24th falling edge. However, if
sequence.
SYNC is brought HIGH before the 24th falling edge, it
acts as an interrupt to the write sequence. The shift
INPUT SHIFT REGISTER
register is reset and the write sequence is seen as
invalid. Neither an update of the DAC register
The input shift register is 24 bits wide, as shown in
contents nor a change in the operating mode occurs,
Figure 47. The first six bits are don't care bits. The
as shown in Figure 48.
next two bits (PD1 and PD0) are control bits that
control which mode of operation the part is in (normal
mode or any one of three power-down modes). For a POWER-ON RESET
more complete description of the various modes see
The DAC8550 contains a power-on reset circuit that
the Power-Down Modes section. The next 16 bits are
controls the output voltage during power-up. On
the data bits. These bits are transferred to the DAC
power-up, the output voltages are set to midscale;
register on the 24th falling edge of SCLK.
they remain that way until a valid write sequence is
made to the DAC. The power-on reset is useful in
applications where it is important to know the state of
the output of the DAC while it is in the process of
powering up.
DB23 DB0
X X X X X X PD PD D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
1 0
Figure 47. DAC8550 Data Input Register Format
Figure 48. SYNC Interrupt Facility
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