Datasheet

DAC
Register
REF(+)
ResistorString
REF( )-
GND
V
REF
V
OUT
62kW
50kW 50kW
V
FB
V
OUT
+
V
REF
2
)
V
REF
D
65536
R
R
R
R
ToOutput
Amplifier
R
DAC8550
www.ti.com SLAS476E –MARCH 2006–REVISED MARCH 2012
THEORY OF OPERATION
DAC SECTION
The architecture of the DAC8850 consists of a string
DAC followed by an output buffer amplifier. Figure 45
shows the block diagram of the DAC architecture.
Figure 45. DAC8550 Architecture
The input coding to the DAC8550 is 2's complement,
so the ideal output voltage is given by:
(1)
where D = decimal equivalent of the 2's complement
code that is loaded to the DAC register; D ranges
from –32768 to +32767 where D = 0 is centered at
V
REF
/2.
RESISTOR STRING
The resistor string section is shown in Figure 46. It is
simply a string of resistors, each of value R. The
Figure 46. Resistor String
code loaded into the DAC register determines at
which node on the string the voltage is tapped off to
SERIAL INTERFACE
be fed into the output amplifier by closing one of the
switches connecting the string to the amplifier.
The DAC8550 has a 3-wire serial interface (SYNC,
Monotonicity is ensured because of the string resistor
SCLK, and D
IN
), which is compatible with SPI, QSPI,
architecture.
and Microwire interface standards, as well as most
DSP interfaces. See the Serial Write Operation timing
OUTPUT AMPLIFIER
diagram for an example of a typical write sequence.
The output buffer amplifier is capable of generating
The write sequence begins by bringing the SYNC line
rail-to-rail output voltages with a range of 0V to V
DD
. It
LOW. Data from the D
IN
line are clocked into the 24-
is capable of driving a load of 2kΩ in parallel with
bit shift register on each falling edge of SCLK. The
1000pF to GND. The source and sink capabilities of
serial clock frequency can be as high as 30MHz,
the output amplifier can be seen in the Typical
making the DAC8550 compatible with high-speed
Characteristics. The slew rate is 1.8V/μs with a full-
DSPs. On the 24th falling edge of the serial clock, the
scale setting time of 8μs with the output unloaded.
last data bit is clocked in and the programmed
function is excuted (that is, a change in DAC register
The inverting input of the output amplifier is brought
contents and/or a change in the mode of operation).
out to the V
FB
pin. This architecture allows for better
accuracy in critical applications by tying the V
FB
point
At this point, the SYNC line may be kept LOW or
and the amplifier output together directly at the load.
brought HIGH. In either case, it must be brought
Other signal conditioning circuitry may also be
HIGH for a minimum of 33ns before the next write
connected between these points for specific
sequence so that a falling edge of SYNC can initiate
applications.
the next write sequence. Since the SYNC buffer
draws more current when the SYNC signal is HIGH
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