Datasheet

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V
REF+
To Output
Amplifier
R
R R
R
V
REF–
OUTPUT AMPLIFIER
PARALLEL INTERFACE
LDAC FUNCTION
DAC8544
SLAS420A – MAY 2004 – REVISED JUNE 2005
THEORY OF OPERATION (continued)
Figure 31. Resistor String
The output buffer is capable of generating rail-to-rail voltages at its output, which gives an output range of 0 V to
V
REF+
. It is capable of driving a load of 2 k Ω in parallel with 1000 pF to GND. The source and sink capabilities of
the output amplifier can be seen in the typical curves. The slew rate is 1 V/ µ s with a full-scale settling time of 10
µ s with the output loaded. The feedback and gain setting resistors of the amplifier are in the order of 50 k Ω . Their
absolute value can be off significantly, but they are matched to within 0.1%.
The inverting input of the output amplifier is brought out to the V
FB
pin, through the feedback resistor. This allows
for better accuracy in critical applications by tying the V
FB
point and the amplifier output together at the load.
Other signal conditioning circuitry may also be connected between these points for specific applications including
current sourcing.
The DAC8544 provides a 16-bit parallel interface and supports both writing to and reading from the DAC input
register. (See the timing characteristics section for detailed information for a typical write or read operation.) In
addition to the data, CS, and R/ W inputs, the DAC8544's interface also provides power down, LDAC, and reset
control. Table 1 to Table 5 show the control signal actions and data format, respectively. These features are
discussed in more detail in the remaining sections.
Table 1. DAC8544 CONTROL SIGNAL SUMMARY
CS R/ W LDAC RST PD ACTION
H X X X X Device data I/O is disabled on the bus.
(1)
↓ L X H,L H Write initiated, external data is latched when writing to the device.
↓ H X H,L H Read initiated, data from input register is presented to data bus.
X X ↑ H,L H Data from input register is transferred to DAC register and V
OUT
is updated.
All DAC registers and voltage outputs (V
OUT
) reset to min-scale. (If DAC is powered down during
X X X ↑ H
reset, DAC registers reset and outputs (V
OUT
) settle to min-scale on power up.)
X X X X L Power down device, V
OUT
impedance equals high impedance
(1) Only disables 16-bit data I/O interface. Other control lines remain active.
The DAC8544 is designed using a double-buffered architecture. A write operation (falling edge of CS while R/ W
is low) transfers data from the data input pins into the input register. The data is held in the input register until a
rising-edge is detected on the LDAC input. This rising-edge signal transfers the data from the input registers to
the DAC registers. On issuance of the rising LDAC edge, the output of the DAC8544 begins settling to the newly
written data value presented to the DAC register. Data in the input register is not changed when an LDAC rising
edge occurs.
Table 2. LDAC Function Section
A1 A0 CS R/W LDAC ACTION
X X X X ↑ All DAC registers are simultaneously loaded with the contents of their corresponding input registers
and all DAC outputs also updated.
13