Datasheet

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SLAS353 − DECEMBER 2001
13
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THEORY OF OPERATION
D/A section
The architecture of the DAC8541 consists of a string DAC followed by an output buffer amplifier. Figure 29
shows a generalized block diagram of the DAC architecture.
REF+
Resistor
String
REF−
V
REF
L = AGND
DAC Register
V
OUT
V
OUT
Sense
V
REF
H = External Reference Voltage
−
+
Figure 29. Generalized DAC Architecture
The input coding to the DAC8541 is set by the BTC/USB
input to the device. When this input is high, the input
code is binary 2s complement. If the input is low, the format is unipolar straight binary, in which case the ideal
output voltage is given by:
V
OUT
+ V
REF
H
D
65536
Where D = the decimal equivalent of the binary code that is loaded to the DAC register, which can range from
0 to 65535 and V
REF
L = AGND.
R
DIVIDE
R
R
R
R
To Output Amplifier
(2x Gain)
V
REF
H
V
REF
L
V
REF
H
2
Figure 30. Typical Resistor String