Datasheet

DAC8534
16
SBAS254D
www.ti.com
DAC8534 to Microwire INTERFACE
Figure 7 shows an interface between the DAC8534 and any
Microwire compatible device. Serial data is shifted out on the
falling edge of the serial clock and is clocked into the
DAC8534 on the rising edge of the CK signal.
DAC8534 to 68HC11 INTERFACE
Figure 8 shows a serial interface between the DAC8534 and
the 68HC11 microcontroller. SCK of the 68HC11 drives the
SCLK of the DAC8534, while the MOSI output drives the
serial data line of the DAC. The
SYNC signal is derived from
a port line (PC7), similar to the 8051 diagram.
FIGURE 6. DAC8534 to 80C51/80L51 Interface.
FIGURE 8. DAC8534 to 68HC11 Interface.
80C51/80L51
(1)
P3.3
TXD
RXD
DAC8534
(1)
SYNC
SCLK
D
IN
NOTE: (1) Additional pins omitted for clarity.
SYNC
SCLK
D
IN
Microwire
TM
CS
SK
SO
DAC8534
(1)
NOTE: (1) Additional pins omitted for clarity.
Microwire is a registered trademark of National Semiconductor.
68HC11
(1)
PC7
SCK
MOSI
SYNC
SCLK
D
IN
DAC8534
(1)
NOTE: (1) Additional pins omitted for clarity.
DAC8534
TMS320 DSP
SYNC
D
IN
SCLK
FSX
DX
CLKX
AV
DD
V
OUT
A
V
OUT
D
Output A
Output D
Reference
Input
V
REF
L
V
REF
H
GND
0.1µF1µF to 10µF
Positive Supply
0.1µF10µF
FIGURE 7. DAC8534 to Microwire Interface.
FIGURE 9. DAC8534 to TMS320 DSP.
APPLICATIONS
CURRENT CONSUMPTION
The DAC8534 typically consumes 250µA at AV
DD
= 5V and
225µA at AV
DD
= 3V for each active channel, including
reference current consumption. Additional current consump-
tion can occur at the digital inputs if V
IH
<< IOV
DD
. For most
efficient power operation, CMOS logic levels are recom-
mended at the digital inputs to the DAC.
In power-down mode, typical current consumption is 200nA
per channel. A delay time of 10ms to 20ms after a power-
down command is issued to the DAC is typically sufficient for
the power-down current to drop below 10µA.
DRIVING RESISTIVE AND CAPACITIVE LOADS
The DAC8534 output stage is capable of driving loads of up
to 1000pF while remaining stable. Within the offset and gain
error margins, the DAC8534 can operate rail-to-rail when
driving a capacitive load. Resistive loads of 2kΩ can be
driven by the DAC8534 while achieving a typical load regu-
lation of 1%. As the load resistance drops below 2kΩ, the
load regulation error increases. When the outputs of the DAC
are driven to the positive rail under resistive loading, the
PMOS transistor of each Class-AB output stage can enter
into the linear region. When this occurs, the added IR voltage
drop deteriorates the linearity performance of the DAC. This
only occurs within approximately the top 20mV of the DAC’s
output voltage characteristic. The reference voltage applied
to the DAC8534 may be reduced below the supply voltage
applied to AV
DD
in order to eliminate this condition if good
linearity is a requirement at full-scale (under resistive loading
conditions).
CROSSTALK AND AC PERFORMANCE
The DAC8534 architecture uses separate resistor strings for
each DAC channel in order to achieve ultra-low crosstalk
performance. DC crosstalk seen at one channel during a full-
The 68HC11 should be configured so that its CPOL bit is 0
and its CPHA bit is 1. This configuration causes data appear-
ing on the MOSI output to be valid on the falling edge of
SCLK. When data is being transmitted to the DAC, the
SYNC line is held LOW (PC7). Serial data from the 68HC11
is transmitted in 8-bit bytes with only eight falling clock edges
occurring in the transmit cycle. (Data is transmitted MSB
first.) In order to load data to the DAC8534, PC7 is left LOW
after the first eight bits are transferred, then a second and
third serial write operation is performed to the DAC. PC7 is
taken HIGH at the end of this procedure.
DAC8534 to TMS320 DSP INTERFACE
Figure 9 shows the connections between the DAC8534 and
a TMS320 Digital Signal Processor (DSP). A Single DSP can
control up to four DAC8534s without any interface logic.