Datasheet

15
DAC8534
SBAS254D
www.ti.com
LDAC FUNCTIONALITY
The DAC8534 offers both a software and hardware simulta-
neous update function. The DAC8534 double-buffered architec-
ture has been designed so that new data can be entered for
each DAC without disturbing the analog outputs. The software
simultaneous update capability is controlled by the Load 1 (LD1)
and Load 0 (LD0) control bits. By setting Load 1 equal to “1” all
of the DAC registers will be updated on the falling edge of the
24th clock signal. When the new data has been entered into the
device, all of the DAC outputs can be updated simultaneously
and synchronously with the clock.
The internal DAC register is edge triggered and not level
triggered, therefore, when the LDAC pin signal is transitioned
from LOW to HIGH, the digital word currently in the DAC input
register is latched. Additionally, it allows the DAC input registers
to be written to at any point; then, the DAC output voltages can
be asynchronously changed via the LDAC pin. The LDAC trigger
should only be used after the buffers are properly updated
through software. If DAC outputs are desired to be updated
through software only, the LDAC pin must be tied low perma-
nently.
Example 4: Power-Down DAC A Through DAC D to High-Impedance Sequentially:
• Write power-down command to Data Buffer A and Load DAC A: DAC A output = High-Z:
A1 A0 LD1 LD0 DC DAC Sel 1 DAC Sel 0 PD0 DB15 DB14 DB13 ........
0001X00111X........
A1 A0 LD1 LD0 DC DAC Sel 1 DAC Sel 0 PD0 DB15 DB14 DB13 ........
0001X01111X........
• Write power-down command to Data Buffer B and Load DAC B: DAC B output = High-Z:
• Write power-down command to Data Buffer C and Load DAC C: DAC C output = High-Z:
A1 A0 LD1 LD0 DC DAC Sel 1 DAC Sel 0 PD0 DB15 DB14 DB13 ........
0001X10111X........
• Write power-down command to Data Buffer D and Load DAC D: DAC D output = High-Z:
MICROPROCESSOR
INTERFACING
DAC8534 to 8051 INTERFACE
See Figure 6 for a serial interface between the DAC8534 and
a typical 8051-type microcontroller. The setup for the inter-
face is as follows: TXD of the 8051 drives SCLK of the
DAC8534, while RXD drives the serial data line of the device.
The
SYNC signal is derived from a bit-programmable pin on
the port of the 8051. In this case, port line P3.3 is used. When
data is to be transmitted to the DAC8534, P3.3 is taken LOW.
The 8051 transmits data in 8-bit bytes; thus only eight falling
clock edges occur in the transmit cycle. To load data to the
DAC, P3.3 is left LOW after the first eight bits are transmitted,
then a second and third write cycle is initiated to transmit the
remaining data. P3.3 is taken HIGH following the completion
of the third write cycle. The 8051 outputs the serial data in a
format which presents the LSB first, while the DAC8534
requires its data with the MSB as the first bit received. The
8051 transmit routine must therefore take this into account,
and “mirror” the data as needed.
A1 A0 LD1 LD0 DC DAC Sel 1 DAC Sel 0 PD0 DB15 DB14 DB13 ........
0001X11111X........
The DAC A, DAC B, DAC C, and DAC D analog outputs sequentially power-down to high-impedance upon completion of the
1st, 2nd, 3rd, and 4th write sequences, respectively.
• Write power-down command to Data Buffer B: DAC B to 1kΩ.
A1 A0 LD1 LD0 DC DAC Sel 1 DAC Sel 0 PD0 DB15 DB14 DB13 ........
0000X01101X........
• Write power-down command to Data Buffer C: DAC C to 100kΩ.
A1 A0 LD1 LD0 DC DAC Sel 1 DAC Sel 0 PD0 DB15 DB14 DB13 ........
0000X10110X........
• Write power-down command to Data Buffer D: DAC D to 100kΩ and Simultaneously Update all DACs.
A1 A0 LD1 LD0 DC DAC Sel 1 DAC Sel 0 PD0 DB15 DB14 DB13 ........
0010X11110X........
The DAC A, DAC B, DAC C, and DAC D analog outputs simultaneously power-down to each respective specified mode upon
completion of the 4th write sequence.