Datasheet

11
DAC8534
SBAS254D
www.ti.com
The write sequence begins by bringing the SYNC line LOW.
Data from the D
IN
line is clocked into the 24-bit shift register on
each falling edge of SCLK. The serial clock frequency can be
as high as 30MHz, making the DAC8534 compatible with high-
speed DSPs. On the 24th falling edge of the serial clock, the
last data bit is clocked into the shift register and the shift
register gets locked. Further clocking does not change the shift
register data. Once 24 bits are locked into the shift register, the
8MSBs are used as control bits and the 16LSBs are used as
data. After receiving the 24th falling clock edge, DAC8534
decodes the 8 control bits and 16 data bits to perform the
required function, without waiting for a
SYNC rising edge. A
new SPI sequence starts at the next falling edge of
SYNC . A
rising edge of
SYNC before the 24-bit sequence is complete
resets the SPI interface; no data transfer occurs.
At this point, the
SYNC line may be kept LOW or brought HIGH.
In either case, the minimum delay time from the 24th falling
SCLK edge to the next falling
SYNC edge must be met in order
to properly begin the next cycle. To assure the lowest power
consumption of the device, care should be taken that the digital
input levels are as close to each rail as possible. (Please refer
to the “Typical Characteristics” section for the “Supply Current
vs Logic Input Voltage” transfer characteristic curve.)
IOV
DD
AND VOLTAGE TRANSLATORS
The IOV
DD
pin powers the digital input structures of the
DAC8534. For single-supply operation, it could be tied to AV
DD
.
For dual-supply operation, the IOV
DD
pin provides interface
flexibility with various CMOS logic families and it should be
connected to the logic supply of the system. Analog circuits and
internal logic of the DAC8534 use AV
DD
as the supply voltage.
The external logic high inputs get translated to AV
DD
by level
shifters. These level shifters use the IOV
DD
voltage as a
THEORY OF OPERATION
DAC SECTION
The architecture of each channel of the DAC8534 consists of
a resistor-string DAC followed by an output buffer amplifier.
Figure 1 shows a simplified block diagram of the DAC
architecture.
The input coding for each device is unipolar straight binary,
so the ideal output voltage is given by:
VX VLVHVL
D
OUT
REF REF REF
IN
=+−••2
65536
()
where D = decimal equivalent of the binary code that is
loaded to the DAC register; it can range from 0 to 65535.
V
OUT
X refers to channel A or through D.
RESISTOR STRING
The resistor string section is shown in Figure 2. It is simply
a divide-by-2 resistor followed by a string of resistors. The
code loaded into the DAC register determines at which node
on the string the voltage is tapped off. This voltage is then
applied to the output amplifier by closing one of the switches
connecting the string to the amplifier.
OUTPUT AMPLIFIER
Each output buffer amplifier is capable of generating rail-to-
rail voltages on its output which approaches an output range
of 0V to AV
DD
(gain and offset errors must be taken into
account). Each buffer is capable of driving a load of 2kΩ in
parallel with 1000pF to GND. The source and sink capabili-
ties of the output amplifier can be seen in the typical charac-
teristics.
SERIAL INTERFACE
The DAC8534 uses a 3-wire serial interface ( SYNC , SCLK,
and D
IN
), which is compatible with SPI™, QSPI™, and
Microwire™ interface standards, as well as most DSPs. See
the Serial Write Operation timing diagram for an example of
a typical write sequence.
FIGURE 1. DAC8534 Architecture.
To Output
Amplifier
(2x Gain)
R
R
R
R
V
REF
2
V
REF
H
R
DIVIDER
V
REF
L
FIGURE 2. Resistor String.
DAC Register
REF (+)
Resistor String
REF(–)
V
REF
H
V
REF
L
V
OUT
50kΩ 50kΩ
70kΩ