Datasheet

DAC8532
12
SBAS246A
www.ti.com
D17 D16
PD1 PD0
01 1kΩ
1 0 100kΩ
1 1 High Impedance
TABLE III. Power-Down Commands.
OUTPUT IMPEDANCE POWERDOWN COMMANDS
00LDBLDAX
Buffer Selec t PD1 PD0 D15 D14 D13 D12
D11D10D9D8D7D6D5D4D3D2D1 D0
DB11 DB0
FIGURE 5. DAC8532 Data Input Register Format.
DB23 DB12
D23 D22 D21 D20 D19 D18 D17 D16
Reserved Reserved Load B Load A Don’t Care Buffer Select PD1 PD0
0 = A, 1 = B
0 0 0 0 X # 0 0 Data WR Buffer # w/Data
0 0 0 0 X # X WR Buffer # w/Power-Down Command
0 0 0 1 X # 0 0 Data WR Buffer # w/Data and Load DAC A
0001X 0 X
WR Buffer A w/Power-Down Command and LOAD DAC A
(DAC A Powered Down)
0 0 0 1 X 1 X WR Buffer B w/Power-Down Command and LOAD DAC A
0 0 1 0 X # 0 0 Data WR Buffer # w/Data and Load DAC B
0 0 1 0 X 0 X WR Buffer A w/Power-Down Command and LOAD DAC B
0010X 1
X WR Buffer B w/ Power-Down Command and LOAD DAC B
(DAC B Powered Down)
0 0 1 1 X # 0 0 Data WR Buffer # w/Data and Load DACs A and B
0011X 0
X WR Buffer A w/Power-Down Command and Load DACs A
and B (DAC A Powered Down)
0011X 1
X WR Buffer B w/Power-Down Command and Load DACs A
and B (DAC B Powered Down)
D15 D14 D13-D0
MSB MSB-1 MSB-2...LSB
(see Table III)
(see Table III)
(see Table III)
(Always Write 0)
TABLE II. Control Matrix.
DESCRIPTION
(see Table III)
(see Table III)
(see Table III)
(see Table III)
SCLK
SYNC
D
IN
Invalid Write-Sync Interrupt:
SYNC HIGH before 24th Falling Edge
Valid Write -Buffer/DAC Update:
SYNC HIGH after 24th Falling Edge
DB23 DB22
12 12
DB0 DB23 DB22 DB1 DB0
24th Falling
Edge
24th Falling
Edge
FIGURE 4. Interrupt and Valid SYNC Timing.