Datasheet

Host Processor Interface
3-7
EVM Operation
For the lowest power operation of the device, the SYNC line should be idled
low between write sequences because the SYNC
buffer draws more current
when the SYNC
signal is high than it does when it is low. Just before another
write sequence is desired, the SYNC
line must be brought high for a minimum
of 33 ns so that a falling edge of the SYNC
can initiate the next write sequence.
3.2.1.3 Serial Data Input (D
IN
)
The serial data input is clocked into the 24-bit shift register from the D
IN
line
on the falling edge of SCLK. The data is shifted in starting with the MSB and
only 18 of the 24 bits are valid. The first 6 MSB are ignored and bits 17 (PD1)
and 16 (PD0) are extracted to determine the DACs mode of operation (see
Table 3–2). The remaining 16 bits are data bits which are transferred to the
DAC register on the 24th falling edge of SCLK.
The external D
IN
signal is fed through J7, pin 36, and is routed to the DAC,
U11, pin 7, through W2 by shorting pins 2 and 3. The header, J10, pin 7, can
also be used to feed the external D
IN
signal when using another type of
processor or microcontroller that does not support the common connector
scheme, but supports the serial interface protocol.
3.2.2 Host Processor Operation
The host processor basically drives the DAC, so the DACs proper operation
depends on the successful configuration between the host processor and the
EVM board, and of course a properly written code to run the DAC.
The EVM incorporates four different options for the DAC output through an
operational amplifier, U12. This requires some jumper setting configuration,
particularly around the op-amp (U12) circuitry, and other required equipment
needed. Each option is discussed individually in the next subsections.
Regardless, the raw output of the DAC can be probed through W13 pin 2 so
that it can be compared with the output of U12 if necessary. The output
terminals J11, J3-1 and TP1 can be used to monitor the raw output of the DAC
by shorting pins 1 and 2 of W13.
3.2.2.1 Unity Gain Output (Default Mode)
The EVM is shipped with the unity-gain output as its default configuration
mode. The buffered output should closely match the raw output of the DAC
with maybe some slight distortion because of the feedback resistor and
capacitor. The user can tailor the feedback circuit to closely match their
desired wave shape by simply desoldering R3 and C27 and replacing it with
the desired values. Also R3 and C27 can be eliminated altogether and a 0-Ω
resistor soldered in replacement of R3, if desired.
Table 3–3 shows the jumper settings relating to the unity gain configuration of
the output buffer.