Datasheet

Host Processor Interface
3-6
J6 and J7, are incorporated into the EVM for direct plug-in to a DSP
development board or starter kit that supports a common connector interface.
However, J8, J9, and J10 headers are provided to allow the user to customize
their interface cable to suit their system configuration. If the DSP development
board or starter kit is used to interface with the EVM board through the
common connector, then supply power to the EVM must be selected through
W9. A voltage supply of 5 V or 3.3 V can be selected depending on the overall
system’s requirement.
When operating the EVM in the host processor mode of testing, make sure to
slide the switches, SW1A and SW1B, to the off position. This will ensure that
the clock and all other digital devices onboard are idled and will not emit
switching noise or any other noise related to the digital parts onboard.
3.2.1 Signal Interface
There are three signals that are essential in the successful operation of the
DAC, which will be covered in detail in this section. These three serial interface
signals are SCLK, SYNC
, and D
IN
, and are compatible with SPI, QSPI,
Microwire, and most DSP serial interfaces.
3.2.1.1 Serial Clock (SCLK)
The serial input clock, SCLK, has a maximum frequency of 30 MHz to be
compatible with high-speed processors. The DSP development board or
starter kit when mated with the EVM through the daughterboard connector
must provide the external clock source.
The external clock source signal is fed through J7 pin 33 and is routed to the
DAC, U11, pin 6, through W3 by shorting pins 2 and 3. The header, J10, pin
3 can also be used to feed the external clock source when using another type
of processor or microcontroller that does not support the common connector
scheme, but supports the serial interface protocol.
3.2.1.2 Synchronization Signal (SYNC
)
The SYNC signal synchronizes the stream of data with the serial clock and
marks the start of the write sequence. When the SYNC line is brought low, the
first falling edge of SCLK is the start of the valid data. The SYNC
line must be
held low for at least 24 SCLK cycles for the write sequence to complete, and
the DAC is updated on the 24th falling edge of SCLK.
If the SYNC
line is brought high before the 24th falling edge of SCLK, the shift
register is reset and the write sequence is terminated or becomes invalid. The
DAC is not updated as well. In essence, this can serve as an interrupt signal
to the DAC.
The external SYNC
signal is fed through J7, pin 35, and is routed to the DAC,
U11 pin 5, through W4 by shorting pins 2 and 3. The header, J10, pin 11 can
also be used to feed the external SYNC
signal when using another type of
processor or microcontroller that does not support the common connector
scheme, but supports the serial interface protocol.