Datasheet

Stand-Alone DC Mode Test
3-4
is again repeated. The timing diagram of the write sequence is shown in
Figure 3–3.
Figure 3–3. Write Sequence Timing Diagram
FC0000
SYNC
SCLK
D
IN
The output of the DAC can be displayed with the use of an oscilloscope by
probing either of the output terminals J11, J3-1, and TP1. Figure 3–4 shows
the normal output for the first power up of the EVM from the factory (default
configuration). This figure shows the zero-scale output of the DAC. Channel
1 presents the DAC output through a unity gain signal conditioning op-amp,
U12. Channel 2 is the DAC output straight out of U11, pin 4, for comparison.
Figure 3–4. Zero-Scale Output
Figure 3–5 shows the half-scale output of the DAC as the switches are
configured to send the data of 0x008000 to the DAC. Channel 1 presents the