DAC8531 Evaluation Module User’s Guide June 2001 AAP Data Acquistion (Dallas) SLAU076
IMPORTANT NOTICE Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue any product or service without notice, and advise customers to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete.
EVM IMPORTANT NOTICE Texas Instruments (TI) provides the enclosed product(s) under the following conditions: This evaluation kit being sold by TI is intended for use for ENGINEERING DEVELOPMENT OR EVALUATION PURPOSES ONLY and is not considered by TI to be fit for commercial use.
EVM WARNINGS AND RESTRICTIONS It is important to operate this EVM within the specified input and output ranges described in the EVM User’s Guide. Exceeding the specified input range may cause unexpected operation and/or irreversible damage to the EVM. If there are questions concerning the input range, please contact a TI field representative prior to connecting the input power.
Information About Cautions and Warnings Preface Read This First About This Manual This user’s guide describes the characteristics, operation, and the use of the DAC8531 Evaluation Module. It covers all pertinent areas involved to properly use this EVM board along with the devices that it supports. The physical PCB layout, schematic diagram, and circuit descriptions are included.
Related Documentation From Texas Instruments Related Documentation From Texas Instruments To obtain a copy of any of the following TI documents, call the Texas Instruments Literature Response Center at (800) 477–8924 or the Product Information Center (PIC) at (972) 644–5580. When ordering, identify this manual by its title and literature number. Updated documents can also be obtained through our website at www.ti.com.
Contents Contents 1 EVM Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.2 Power Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.2.1 Supply Voltage . . . . . . . . . . . . . . . . . . . . .
Contents Figures 1–1 2–1 2–2 2–3 2–4 2–5 2–6 2–7 2–8 2–9 3–1 3–2 3–3 3–4 3–5 3–6 3–7 3–8 3–9 3–10 EVM Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-4 Top Assembly . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-2 Bottom Assembly . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Chapter 1 EVM Overview This chapter presents a general overview of the DAC8531 evaluation module (EVM), and describes some of the factors that must be considered in using this module. Topic Page 1.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-2 1.2 Power Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-2 1.3 EVM Basic Functions . . . . . . . . . . . . . . . . . . . . . . . . .
Features 1.1 Features This EVM features the DAC8531 digital-to-analog converter. It was specifically designed for the DAC8531, but can also accommodate the DAC8501, DAC7513, and DAC7512. The digital-to-analog converter device that is installed onto the board determines the version of this EVM as shown in the table below. Although this EVM is shipped from factory with the DAC8531, the table below shows the different DAC devices that can be installed as an option to the user. Table 1–1.
EVM Basic Functions If this EVM is used to connect to a DSP evaluation board through the common connectors, J6 and J7, the DSP evaluation board supplies the power for the EVM through J6 and J7. The jumper W9 is provided to allow the 3.3-V and 5.5-V supply to be selected individually by the user. Caution If using an external power supply via J2, remove jumper W9 to avoid potential damage to the DSP circuitry.
EVM Basic Functions common connector headers. Refer to the accompanying DSK manual for proper orientation. If the TI DSK does not map out correctly with the EVM’s common connector headers, then a smart adapter, SPRA711 adapter, can be used. The smart adapter routes the necessary signals properly with ease by correctly configuring the adapter board for the DSK being used. A precision reference voltage is provided onboard, which can be adjusted to the user’s preference through the R29 potentiometer.
Chapter 2 Physical Description This chapter describes the physical characteristics and PCB layout of the EVM and lists the components used on the module. Topic Page 2.1 PCB Layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-2 2.2 Bill of Materials . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PCB Layout 2.1 PCB Layout The EVM is constructed on a four-layer printed circuit board using a copperclad FR-4 laminate material. The printed circuit board has a dimensions of 147,828 mm (5.82 inch) × 86,106 mm (3.39 inch), and the board thickness is 1,57 mm (0.062 inch). Figures 2–1 through 2–9 show the individual artwork layers. Figure 2–1. Top Assembly Figure 2–2.
PCB Layout Figure 2–3. Layer 1 (Silkscreen Top) Figure 2–4.
PCB Layout Figure 2–5. Layer 3 (Power Plane) Figure 2–6.
PCB Layout Figure 2–7. Top Paste Figure 2–8.
PCB Layout Figure 2–9. Drill Layer (Mechanical Specifications) Notes: 1) PWB to be fabricated to meet or exceed IPC-6012, Class 2 standards and workmanship shall conform to IPC-A-600, Class 2—current revisions. 2) Board material and construction to be UL approved and marked on the finished board. 3) Laminate material: copper-clad FR-4 4) Copper weight: 1 oz finished—all layers 5) Finished thickness: 0.062 ±0.010 inch 6) Minimum plating thickness in through holes: 0.
Bill of Materials 2.2 Bill of Materials Table 2–1. Parts Lists Item No. Qty. Designator Description Manufacturer Part Number 1 22 C1, C2, C3, C4, C5, C6, C7, C8, C9, C10, C11, C12, C13, C14, C15, C16, C17, C18, C19, C20, C45, C46 0.1-µF Multilayer ceramic capacitor Panasonic or equivalent ECJ3VB1C104K 2 3 C24, C25, C26 0.
Bill of Materials Table 2–1. Parts List (Continued) Item No. Qty. 25 2-8 Designator Description Manufacturer Part Number 2 R4, R24 510-Ω, 1/4-W 1206 chip resistor Panasonic or equivalent ERJ-8GEYJ511V 26 1 R5 1-kΩ, 1/4-W, 1206 chip resistor Panasonic or equivalent ERJ-8GEYJ102V 27 3 R6, R7, R15 4.7-kΩ, Panasonic EXB-A/CTS 745 Series Panasonic or equivalent EXBA10P472J 28 1 R26 4.
Bill of Materials Table 2–1. Parts List (Continued) Item No. Qty. Designator Description Manufacturer Part Number 48 2 U14, U15 5-V Precision voltage reference Texas Instruments Incorporated REF02AU 49 1 U16 5-V Thaler precision voltage regulator Thaler Corporation VRE3050JS 50 1 U17 Operation amplifier Texas Instruments Incorporated OPA177GS 51 1 W13 3-Pin dual row header Samtec or equivalent TSW-103-07-L-D 52 9 W2, W3, W4, W5, W6, W7. S8, W9. S14 3-Position jumper, 0.
2-10
Chapter 3 EVM Operation This chapter covers in detail the operation of the EVM to provide guidance to the user in evaluating the onboard DAC and how to interface the EVM to a specific host processor. Refer to the DAC8531 data sheet, SBAS192, for information about the serial interface and other related topics. The EVM board is factory tested and configured in such a way that it should work immediately in stand-alone dc mode with just the slide of a switch. Topic Page 3.1 Stand-Alone Mode Test . . . . .
Stand-Alone DC Mode Test 3.1 Stand-Alone DC Mode Test The stand-alone mode (SAM) test is performed only in dc mode to quickly verify the EVM board for proper functionality. Apply a dc power source of 3.3 V to 5 V with the +supply connecting to J2–2 and referenced to J2–1. The power indicator light, D3, should illuminate (green) once the power is applied. To put the EVM board into stand-alone (or self-test) mode, the SW1B and SW1A switches must be on.
Stand-Alone DC Mode Test the complete mapping of the respective switches to the data input register for either DAC8531 or DAC8501. SW3A and SW3B maps out to PD1 (DB13) and PD0 (DB12) respectively of the DAC data input register (12-bit version). Figure 3–2 shows it for the 12-bit version (DAC7512/13). Table 3–2.
Stand-Alone DC Mode Test is again repeated. The timing diagram of the write sequence is shown in Figure 3–3. Figure 3–3. Write Sequence Timing Diagram SYNC SCLK 0 0 F C 0 0 DIN The output of the DAC can be displayed with the use of an oscilloscope by probing either of the output terminals J11, J3-1, and TP1. Figure 3–4 shows the normal output for the first power up of the EVM from the factory (default configuration). This figure shows the zero-scale output of the DAC.
Host Processor Interface DAC output through a unity gain signal conditioning op-amp, U12, and channel 2 is the DAC output straight out of U11, pin 4, for comparison. Figure 3–5. Half-Scale Output Figure 3–6 shows the full-scale output of the DAC as the switches are configured to send the data of 0x00FC00 to the DAC. Channel 1 presents the DAC output through a unity gain signal conditioning op-amp, U12, and channel 2 is the DAC output straight out of U11, pin 4, for comparison. Figure 3–6.
Host Processor Interface J6 and J7, are incorporated into the EVM for direct plug-in to a DSP development board or starter kit that supports a common connector interface. However, J8, J9, and J10 headers are provided to allow the user to customize their interface cable to suit their system configuration. If the DSP development board or starter kit is used to interface with the EVM board through the common connector, then supply power to the EVM must be selected through W9. A voltage supply of 5 V or 3.
Host Processor Interface For the lowest power operation of the device, the SYNC line should be idled low between write sequences because the SYNC buffer draws more current when the SYNC signal is high than it does when it is low. Just before another write sequence is desired, the SYNC line must be brought high for a minimum of 33 ns so that a falling edge of the SYNC can initiate the next write sequence. 3.2.1.
Host Processor Interface Table 3–3. Unity Gain Output Jumper Settings Reference Jumper Function Setting W7 1–2 + Rail of the op-amp supplied by VCCA W8 1–2 – Rail of the op-amp tied to analog GND W10 Open Disconnect VREF from negative input of op-amp W11 Open Disconnect negative input of op-amp from GND W13 3–4 3.2.2.2 Buffered output of DAC is channeled to the output terminals Output Gain of Two If the EVM is operating at 3.
Host Processor Interface Table 3–5. Capacitive Load Drive Output Jumper Settings Reference Jumper Setting W7 2–3 Select 5 V for the positive rail supply of the op-amp if W12 is closed W8 1–2 Negative rail of the op-amp tied to analog GND W10 Open Disconnect VREF from negative input of op-amp W11 Open (see Note) W12 Close W13 5–6 Note: 3.2.
Host Processor Interface Table 3–6. Bipolar Operation Output Jumper Settings Reference Jumper Setting W7 2–3 Select 5 V for the positive rail supply of U12 if W12 is closed W8 2–3 Select –5 V for the negative supply rail of U12 if W12 is closed W10 Closed W11 Open Disconnect R12 W12 Close Supplies the constant 5 V to the positive rail of U12 and is also fed into the negative input of U17 to generate an output voltage of –5 V.
Jumper Setting 3.3 Jumper Setting The table below lists the function of each jumper on the EVM. Table 3–7. Jumper Setting Function Reference Jumper Setting Function 1 3 1 3 1 3 1 3 1 3 1 3 1 3 Generates a SYNC signal for stand-alone mode after 24 SCLK cycles (default mode). 1 3 Generates a SYNC signal for stand-alone mode after 16 SCLK cycles (used only for 12-bit DACs described in table 1–1).
I/O Signal Mapping Table 3–7. Jumper Setting Function (Continued) Reference Jumper Setting Function Disconnects VREF from the negative input terminal of U12. W10 Allows VREF to be routed to the negative input terminal of U12 for bipolar operation. Disconnect the negative terminal of U12 to AGND. W11 Allow a 2× gain output in unipolar mode. Disconnects 12-V supply to U15 or R22 and R23 voltage divider circuit. W12 Connects 12-V supply to U15 or R22 and R23 voltage divider circuit.
I/O Signal Mapping Figure 3–9. Daughterboard Connector Signal Mapping 5V DGND 5V DGND DGND 3.3 V DGND DGND DGND DGND 3.4.2 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 51 53 55 57 59 61 63 65 67 69 71 73 75 77 79 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52 54 56 58 60 62 64 66 68 70 72 74 76 78 80 5V DGND 5V DGND 5V DGND 3.3 V 5V DGND DGND DGND 3.
Schematic Diagram Figure 3–10. DSP and Microcontroller Signal Mapping J8 3.4.3 J9 J10 20 19 20 19 20 19 18 16 14 12 10 8 6 4 2 17 15 13 11 9 7 5 3 1 18 16 14 12 10 8 6 4 2 17 15 13 11 9 7 5 3 1 18 16 14 12 10 8 6 4 2 17 15 13 11 9 7 5 3 1 CLKS FSR FSX DR DX CLKR CLKX DAC Output Connector The DAC output is routed to the J3 pin 1 header as well as the J11 SMA jack. 3.5 Schematic Diagram The following pages show the complete schematic diagram of the DAC8531 evaluation module board.
1 2 3 4 5 6 Revision History REV ECN Number Approved D D VCCD VCCA Power and Reference Module DAC Module serialDAC_2.sch +Supply 1 J1 -15 Supply FS FS +5V Supply +15 Supply 2 1 DAC_VREF +5V DSP_+3.3V +15 Supply VREF VREF DSP_+5V 3 Analog VCC +Supply 2 Digital VCC J2 DAC_FS SCLK SCLK -5V Supply DAC_SCLK SDI SDI J11 VOUT VOUT DAC_DIN -5V -15 Supply C C J3 1 3 5 7 9 11 13 15 17 19 21 23 25 User Interface Module serialDAC_3.sch DSP_+3.3V DSP_+5V DSP_+3.
1 2 3 4 5 6 Revision History VCCD REV GO SAM_SCLK D 1 9 10 7 2 3 4 5 6 16 VCCD SAM_SCLK CLR LOAD ENT ENP CLK A B C D 15 RCO Q24 VCCD 14 13 12 11 QA QB QC QD VCC RCO1 /QA1 /QB1 /QC1 QD1 4 3 2 1 14 PRE CLK D CLR Q Q VCC GND SAM_FS 5 6 Approved SAM_FS 7 SN74AHC74 C12 0.1uF D 8 GND VCCD VCCD SN74HC163 C1 ECN Number U3A GO U1 0.
1 2 3 4 5 6 Revision History REV ECN Number Approved D D VCCA C10 C21 10uF 0.1uF VCCA U11 VDD 5 FS DAC_FS SYNC VFB C W7 1 TP1 C24 3 R10 0.01uF 7 C +5V 0 SCLK DAC_SCLK 6 SCLK VOUT R28 4 3 U12 0 DIN VREF R2 2 C9 0.1uF 10K C22 10uF A1 B3 C5 VOUT VOUT OPA350 W10 4 GND 8 CLD_OUT 2 W13 5 DAC_DIN 7 2 4 6 1 SDI 6 DAC8531 2 4 6 8 B 100K Optional W8 DAC_VREF 1 3 5 7 R11 VREF J5 C25 B 0.
1 2 4 SDI_D10 SDI_D11 SDI_D12 SDI_D13 SDI_D14 SDI_D15 SDI_D16 SDI_D17 SDI_D10 SDI_D11 SDI_D12 SDI_D13 SDI_D14 SDI_D15 SDI_D16 SDI_D17 D 3 5 6 TMS320 Common Connector Interface D DSP_+5V DSP_+5V TP2 J6 VCCD R15A 3 4 1 2 12-bit MSB 12-bit Control Bits Note: Switch ON = 1 2 16-bit MSB 16-bit Control Bits C 1 3 4 SW2A SW2B SW2C SW2D SW3A SW3B SW3C SW3D 8 SDI_D17 R15B 7 SDI_D16 R15C 6 SDI_D15 DSP_+3.
1 2 3 4 5 6 +5V Supply W12 U14 6 3 1 TRIM OUT V+ TEMP NC NC NC 4 VCCA D REF02AU(8) R22 R23 150K 100K +5V D GND 5 2 8 7 L1 R14 10K -15V 15uH U16 VRE3050 D3 REF 3 SS OUT FB 5 GND + C31 33uF COMP 2 1N5817 7 4 VIN OUT 6 4.7uH 6 GREEN R24 500 L2 8 C28 1nF + C32 33uF C23 10uF 8 C13 0.1uF 4 TRIM R25 10K 5 TRIM OUT V+ TEMP NC NC NC C11 0.1uF NR GND C45 0.
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