Datasheet
DAC8531
3
SBAS192B
www.ti.com
LOGIC INPUTS
(2)
Input Current ±1 µA
V
IN
L, Input LOW Voltage V
DD
= +5V 0.8 V
V
IN
L, Input LOW Voltage V
DD
= +3V 0.6 V
V
IN
H, Input HIGH Voltage V
DD
= +5V 2.4 V
V
IN
H, Input HIGH Voltage V
DD
= +3V 2.1 V
Pin Capacitance 3pF
POWER REQUIREMENTS
V
DD
2.7 5.5 V
I
DD
(normal mode)
DAC Active and Excluding Load Current
V
DD
= +3.6V to +5.5V V
IH
= V
DD
and V
IL
= GND 250 400 µA
V
DD
= +2.7V to +3.6V V
IH
= V
DD
and V
IL
= GND 240 390 µA
I
DD
(all power-down modes)
V
DD
= +3.6V to +5.5V V
IH
= V
DD
and V
IL
= GND 0.2 1 µA
V
DD
= +2.7V to +3.6V V
IH
= V
DD
and V
IL
= GND 0.05 1 µA
POWER EFFICIENCY
I
OUT
/I
DD
I
LOAD
= 2mA, V
DD
= +5V 89 %
TEMPERATURE RANGE
Specified Performance –40 +105 °C
PARAMETER CONDITIONS MIN TYP MAX UNITS
ELECTRICAL CHARACTERISTICS (Cont.)
V
DD
= +2.7V to +5.5V. –40°C to +105°C, unless otherwise specified.
DAC8531E
PIN NAME DESCRIPTION
1V
DD
Power-Supply Input, +2.7V to +5.5V.
2V
REF
Reference Voltage Input
3V
FB
Feedback connection for the output amplifier.
4V
OUT
Analog output voltage from DAC. The output ampli-
fier has rail-to-rail operation.
5 SYNC Level-triggered control input (active LOW). This is
the frame sychronization signal for the input data.
When SYNC goes LOW, it enables the input shift
register and data is transferred in on the falling
edges of the following clocks. The DAC is updated
following the 24th clock cycle unless SYNC is taken
HIGH before this edge, in which case the rising
edge of SYNC acts as an interrupt and the write
sequence is ignored by the DAC8531.
6 SCLK Serial Clock Input. Data can be transferred at rates
up to 30MHz.
7D
IN
Serial Data Input. Data is clocked into the 24-bit
input shift register on the falling edge of the serial
clock input.
8 GND Ground reference point for all circuitry on the part.
PIN DESCRIPTION
PIN CONFIGURATIONS
Top View
V
DD
V
REF
V
FB
V
OUT
GND
D
IN
SCLK
SYNC
1
2
3
4
8
7
6
5
DAC8531
MSOP-8
1
2
3
4
8
7
6
5
GND
D
IN
SCLK
SYNC
V
DD
V
REF
V
FB
V
OUT
DAC8531
SON-8