Datasheet

80C51/80L51
(1)
P3.3
TXD
RXD
DAC8x11
(1)
SYNC
SCLK
D
IN
NOTE:(1)Additionalpinsomittedforclarity.
68HC11
(1)
PC7
SCK
MOSI
SYNC
SCLK
D
IN
DAC8x11
(1)
NOTE:(1)Additionalpinsomittedforclarity.
SYNC
SCLK
D
IN
Microwire
CS
SK
SO
DAC8x11
(1)
NOTE: (1) Additional pins omitted for clarity.
DAC8311
DAC8411
SBAS439B –AUGUST 2008–REVISED MAY 2013 www.ti.com
MICROPROCESSOR INTERFACING
DAC8x11 to 8051 Interface
Figure 79 shows a serial interface between the
DAC8x11 and a typical 8051-type microcontroller.
The setup for the interface is as follows: TXD of the
8051 drives SCLK of the DAC8x11, while RXD drives
the serial data line of the part. The SYNC signal is
Figure 80. DAC8x11 to Microwire Interface
derived from a bit programmable pin on the port. In
this case, port line P3.3 is used. When data are to be
transmitted to the DAC8x11, P3.3 is taken low. The
DAC8x11 to 68HC11 Interface
8051 transmits data only in 8-bit bytes; thus, only
eight falling clock edges occur in the transmit cycle.
Figure 81 shows a serial interface between the
To load data to the DAC, P3.3 remains low after the
DAC8x11 and the 68HC11 microcontroller. SCK of
first eight bits are transmitted, and a second write
the 68HC11 drives the SCLK of the DAC8x11, while
cycle is initiated to transmit the second byte of data.
the MOSI output drives the serial data line of the
P3.3 is taken high following the completion of this
DAC. The SYNC signal is derived from a port line
cycle. The 8051 outputs the serial data in a format
(PC7), similar to what was done for the 8051.
which has the LSB first. The DAC8x11 requires its
data with the MSB as the first bit received. Therefore,
the 8051 transmit routine must take this requirement
into account, and mirror the data as needed.
Figure 81. DAC8x11 to 68HC11 Interface
The 68HC11 should be configured so that its CPOL
bit is a '0' and its CPHA bit is a '1'. This configuration
Figure 79. DAC8x11 to 80C51/80L51 Interfaces
causes data appearing on the MOSI output to be
valid on the falling edge of SCK. When data are
DAC8x11 to Microwire Interface
being transmitted to the DAC, the SYNC line is taken
low (PC7). Serial data from the 68HC11 are
Figure 80 shows an interface between the DAC8x11
transmitted in 8-bit bytes with only eight falling clock
and any Microwire-compatible device. Serial data are
edges occurring in the transmit cycle. Data are
shifted out on the falling edge of the serial clock and
transmitted MSB first. In order to load data to the
are clocked into the DAC8x11 on the rising edge of
DAC8x11, PC7 is held low after the first eight bits are
the SK signal.
transferred, and a second serial write operation is
performed to the DAC; PC7 is taken high at the end
of this procedure.
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