Datasheet

CLK
SYNC
D
IN
ValidWriteSequence:
Output/ModeUpdates onthe18thor24thFallingEdge
18thFallingEdge 18th/24thFallingEdge
DB23
Invalid/InterruptedWriteSequence:
Output/ModeDoesNotUpdate onthe18thFallingEdge
DB6 DB5
DB0 DB23 DB6 DB5 DB0
18 2418 24
DAC8311
DAC8411
www.ti.com SBAS439B –AUGUST 2008–REVISED MAY 2013
SERIAL INTERFACE (for 16-Bit DAC8411) At this point, the SYNC line may be kept low or
brought high. In either case, it must be brought high
for a minimum of 20ns before the next write
The DAC8411 has a 3-wire serial interface (SYNC,
sequence so that a falling edge of SYNC can initiate
SCLK, and DIN) compatible with SPI, QSPI, and
the next write sequence. As previously mentioned, it
Microwire interface standards, as well as most DSPs.
must be brought high again before the next write
See the 16-bit Serial Write Operation timing diagram
sequence.
for an example of a typical write sequence.
The SYNC line may be brought high after the 18th bit
DAC8411 Input Shift Register
is clocked in because the last six bits are don't care.
The input shift register is 24 bits wide, as shown in
DAC8411 SYNC Interrupt
Table 3. The first two bits are reserved control bits
(PD0 and PD1) that set the desired mode of
In a normal write sequence, the SYNC line is kept
operation (normal mode or any one of three power-
low for 24 falling edges of SCLK and the DAC is
down modes) as indicated in Table 4. The last six bits
updated on the 18th falling edge, ignoring the last six
are don't care.
don't care bits. However, bringing SYNC high before
the 18th falling edge acts as an interrupt to the write
The write sequence begins by bringing the SYNC line
sequence. The shift register is reset and the write
low. Data from the DIN line are clocked into the 24-bit
sequence is seen as invalid. Neither an update of the
shift register on each falling edge of SCLK. The serial
DAC register contents or a change in the operating
clock frequency can be as high as 50MHz, making
mode occurs, as shown in Figure 75.
the DAC8411 compatible with high-speed DSPs. On
the 18th falling edge of the serial clock, the last data
bit is clocked in and the programmed function is
executed. The last six bits are don't care.
Table 3. DAC8411 Data Input Register
DB2 DB DB DB DB
3 7 6 5 0
PD1 PD0 D1 D1 D1 D1 D1 D1 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 X X X X X X
5 4 3 2 1 0
Figure 75. DAC8411 SYNC Interrupt Facility
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