Datasheet
InvalidWriteSequence:
HIGHbefore16thFallingEdgeSYNC
ValidWriteSequence:
OutputUpdateson16thFallingEdge
CLK
SYNC
D
IN
DB15 DB0 DB15 DB0
DAC8311
DAC8411
SBAS439B –AUGUST 2008–REVISED MAY 2013
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SERIAL INTERFACE (for 14-Bit DAC8311) At this point, the SYNC line may be kept low or
brought high. In either case, it must be brought high
The DAC8311 has a 3-wire serial interface (SYNC,
for a minimum of 20ns before the next write
SCLK, and DIN) compatible with SPI, QSPI, and
sequence so that a falling edge of SYNC can initiate
Microwire interface standards, as well as most DSPs.
the next write sequence. As previously mentioned, it
See the 14-bit Serial Write Operation timing diagram
must be brought high again before the next write
for an example of a typical write sequence.
sequence.
DAC8311 Input Shift Register
DAC8311 SYNC Interrupt
The input shift register is 16 bits wide, as shown in
In a normal write sequence, the SYNC line is kept
Table 2. The first two bits (PD0 and PD1) are
low for at least 16 falling edges of SCLK and the DAC
reserved control bits that set the desired mode of
is updated on the 16th falling edge. However,
operation (normal mode or any one of three power-
bringing SYNC high before the 16th falling edge acts
down modes) as indicated in Table 4.
as an interrupt to the write sequence. The shift
register is reset and the write sequence is seen as
The write sequence begins by bringing the SYNC line
invalid. Neither an update of the DAC register
low. Data from the DIN line are clocked into the 16-bit
contents or a change in the operating mode occurs,
shift register on each falling edge of SCLK. The serial
as shown in Figure 74.
clock frequency can be as high as 50MHz, making
the DAC8311 compatible with high-speed DSPs. On
the 16th falling edge of the serial clock, the last data
bit is clocked in and the programmed function is
executed.
Table 2. DAC8311 Data Input Register
DB15 DB14 DB0
PD1 PD0 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
Figure 74. DAC8311 SYNC Interrupt Facility
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