Datasheet

V
REF
R
R
R
R
ToOutput
Amplifier
R
DIVIDER
V
2
REF
V
OUT
+ AV
DD
D
2
n
REF(+)
ResistorStringDACRegister
GND
Output
Amplifier
V
OUT
AV
DD
DAC8311
DAC8411
www.ti.com SBAS439B –AUGUST 2008–REVISED MAY 2013
THEORY OF OPERATION
DAC SECTION
The DAC8311 and DAC8411 are fabricated using TI's
proprietary HPA07 process technology. The
architecture consists of a string DAC followed by an
output buffer amplifier. Because there is no reference
input pin, the power supply (AV
DD
) acts as the
reference. Figure 72 shows a block diagram of the
DAC architecture.
Figure 72. DAC8x11 Architecture
The input coding to the DAC8311 and DAC8411 is
straight binary, so the ideal output voltage is given by:
Where:
n = resolution in bits; either 14 (DAC8311) or 16
(DAC8411).
D = decimal equivalent of the binary code that is
Figure 73. Resistor String
loaded to the DAC register; it ranges from 0 to
16,383 for the 14-bit DAC8311, or 0 to 65,535 for
the 16-bit DAC8411.
OUTPUT AMPLIFIER
RESISTOR STRING
The output buffer amplifier is capable of generating
rail-to-rail voltages on its output which gives an output
The resistor string section is shown in Figure 73. It is
range of 0V to AV
DD
. It is capable of driving a load of
simply a string of resistors, each of value R. The
2kΩ in parallel with 1000pF to GND. The source and
code loaded into the DAC register determines at
sink capabilities of the output amplifier can be seen in
which node on the string the voltage is tapped off to
the Typical Characteristics section for each device.
be fed into the output amplifier by closing one of the
The slew rate is 0.7V/μs with a half-scale settling time
switches connecting the string to the amplifier. It is
of typically 6μs with the output unloaded.
tested monotonic because it is a string of resistors.
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