Datasheet
PIN CONFIGURATIONS
CS
SCLK
SDI
SDO
LDAC
RST
GPIO-0
GPIO-1
UNI/BIP-A
DGND
AV
DD
V
MON
AV
SS
REFGND-B
REF-B
REF-A
REFGND-A
AV
SS
AGND
AV
DD
1
2
3
4
5
6
7
8
9
10
30
29
28
27
26
25
24
23
22
21
DAC8234
UNI/BIP-B
AIN
V -2
O
UT
R -2
FB2
R -2
FB1
SGND-2
SGND-3
R -3
FB1
R -3
F
B2
V
-3
OUT
40
39
38
37
36
35
34
33
32
31
IOV
D
D
DV
DD
V -0
OU
T
R -0
FB2
R -0
FB1
SGND-0
SGND-1
R -1
FB1
R -1
FB2
V
-1
OUT
11
12
13
14
15
16
17
18
19
20
24
23
22
21
20
19
18
17
16
15
14
13
NC
V -1
OUT
R -1
FB2
R -1
FB1
SGND-1
NC
SGND
-0
R -0
FB1
R -0
FB2
V -0
OUT
DV
DD
IOV
DD
NC
AV
DD
V
MON
AV
SS
REFGND-B
REF-B
REF-A
REFGND-A
AV
SS
AGND
AV
DD
NC
36
35
34
33
32
31
30
29
28
27
26
25
1
2
3
4
5
6
7
8
9
10
11
12
NC
CS
SCLK
SDI
SDO
LDAC
RST
GPIO-0
GPIO-1
UNI/BIP-A
DGND
NC
37
38
39
40
41
42
43
44
45
46
47
48
NC
V -3
O
UT
R -3
FB2
R -3
FB1
SGND-3
NC
SGND
-2
R -2
FB1
R -2
FB2
V
-2
OUT
AIN
UNI/BIP-B
DAC8234
DAC8234
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........................................................................................................................................... SBAS464A – AUGUST 2009 – REVISED SEPTEMBER 2009
RHA PACKAGE
(1)
PFB PACKAGE
QFN-40
TQFP-48
(TOP VIEW)
(TOP VIEW)
(1) The thermal pad is internally connected to
the substrate. This pad can be connected
to AV
SS
or left floating.
PIN DESCRIPTIONS
PIN NO.
PIN
NAME QFN-40 TQFP-48 I/O DESCRIPTION
SPI bus chip select input (active low). Data are not clocked into the SPI shift register unless CS is
CS 1 2 I
low. When CS is high, SDO is in a high-impedance state.
SCLK 2 3 I SPI bus clock
SDI 3 4 I SPI bus input data
SDO 4 5 O SPI output data
Load DAC latch control input (active low). When LDAC is low, the DAC latch is transparent and the
LDAC 5 6 I contents of the Input Data Register are transferred to it. The DAC output changes to the
corresponding level simultaneously when the DAC latch is updated.
Reset input (active low). Logic low on this pin resets the input registers and DACs to the values
RST 6 7 I
defined by the UNI/BIP pins, and sets the Gain Register and Zero Register to default values.
General-purpose digital input/output 0. This pin is a bidirectional, digital input/output, and has an
GPIO-0 7 8 I/O open-drain output. A 10k Ω pull-up resistor to IOV
DD
is needed when this pin is used as an output.
See the GPIO Pins section for details.
General-purpose digital input/output 1. This pin is a bidirectional, digital input/output, and has an
GPIO-1 8 9 I/O open-drain output. A 10k Ω pull-up resistor to IOV
DD
is needed when this pin is used as an output.
See the GPIO Pins section for details.
Output mode selection of group A (DAC-0 and DAC-1). When UNI/BIP-A is tied to IOV
DD
, group A
is in unipolar output mode; when tied to DGND, group A is in bipolar output mode. The input data
UNI/BIP-A 9 10 I
written to the DAC are straight binary for unipolar output mode and twos complement for bipolar
output mode.
DGND 10 11 I Digital ground
IOV
DD
11 13 I Interface power
DV
DD
12 14 I Digital power
V
OUT
-0 13 15 O DAC-0 output
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