Datasheet
System Zero Adjust Example
- ´1 Offset_Error
StepSize
NumberofStepsofZeroCalibration=
(3)
System Gain Adjust Example
- ´1 Gain_Error
StepSize
NumberofStepsofGainCalibration=
(4)
DAC8234
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........................................................................................................................................... SBAS464A – AUGUST 2009 – REVISED SEPTEMBER 2009
The DAC8234 zero calibration feature can minimize system offset errors to 0.00019% FSR or 38 µ V over a 20V
output range. The total adjustment range is approximately ± 0.0488% of FSR, or ± 9.7mV over a 20V output span.
Assuming that the DAC has been set up with a full-scale range of 20V, and the offset error to be eliminated from
the signal chain is – 1mV, then the step size = 0.0000019 × 20V = 38 µ V.
Where Offset_Error is the value of the offset error to be corrected.
For this example, the number of steps of zero calibration = 1mV / 38 µ V ≈ 26. Therefore, the Zero Register should
be coded with the twos complement of 26 = 0 0001 1010.
Suppose the offset error to be eliminated is +1mV instead; then the number of steps of zero calibration is the
twos complement equivalent of – 26, which is 1 1110 0110.
The DAC8234 gain calibration feature can minimize system gain errors to 0.001525% FSR or 305 µ V over a 20V
output range. The total adjustment range is approximately ± 0.195% FSR, or – 39mV to +38.7mV over a 20V
output span.
Assuming that the DAC has been set up with a full-scale range of 20V, and the gain error to be eliminated from
the signal chain is – 10mV, then the step size = 0.00001525 × 20V = 305 µ V.
Where Gain_Error is the value of the gain error to be corrected.
For this example, the number of steps of the gain calibration = 10mV/305 µ V ≈ 33. Therefore, the Gain Register
should be coded with the twos complement of 33 = 0010 0001.
Suppose the gain error to be eliminated is +10mV instead; then the number of steps of Gain calibration is the
twos complement equivalent of – 33, which is 1101 1111.
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