Datasheet

INTERNAL REGISTERS
DAC8234
SBAS464A – AUGUST 2009 – REVISED SEPTEMBER 2009 ........................................................................................................................................... www.ti.com
The DAC8234 internal registers consist of the Command Register, the Monitor Register, the DAC Input Data
Registers, the Zero Registers, and the Gain Registers.
Command Register. Default = 033Ch.
The Command Register determines the actions performed by the DAC8234.
Table 4. Command Register
DEFAULT
BIT NAME VALUE DESCRIPTION
A/B bit.
DB15 A/B 0 When A/B = '0', reading DAC-x returns the value in the Input Data Register.
When A/B = '1', reading DAC-x returns the value in the DAC latch.
Synchronously update DACs bit. Functions in the same manner as the LDAC pin.
When LDAC is tied high, set LD = '1' at any time after the write operation and the correction process proceeds to
synchronously update all DAC latches with the content of the corresponding Input Data Register, and sets V
OUT
to a new
DB14 LD 0 level. The DAC8234 updates the DAC latch only if it has been accessed since the last time LDAC was brought low or the
LD bit was set to '1', thereby eliminating unnecessary glitch. Any DACs that were not accessed are not reloaded. After
updating, the bit returns to '0'. Refer to the Updating Via LDAC section for details.
When the LDAC pin is tied low, the LD bit is ignored.
Software reset bit.
DB13 RST 0 Set the RST bit to '1' to reset the device; functions the same as a hardware reset. After reset completes, the RST bit
returns to '0'.
Power-down bit for Group A.
Setting the PD-A bit to '1' places Group A (DAC-0 and DAC-1) into power-down operation. All output buffers are in Hi-Z
DB12 PD-A 0
and all analog outputs (V
OUT
-x) connect to AGND through an internal 10k Ω resistor. The interface remains active.
Setting the PD-A bit to '0' returns Group A to normal operation.
Power-down bit for Group B.
Setting the PD-B bit to '1' places Group B (DAC-2 and DAC-3) into power-down operation. All output buffers are in Hi-Z
DB11 PD-B 0
and all analog outputs (V
OUT
-x) connect to AGND through an internal 10k Ω resistor. The interface remains active.
Setting the PD-B bit to '0' returns Group B to normal operation.
DB10 Rsvd 0 Reserved. Writing to this bit has no effect; reading this bit returns '0'.
GPIO-1 status bit.
Writing a '1' to the GPIO-1 bit puts the GPIO-1 pin into a Hi-Z state (default).
DB9 GPIO-1 1
Writing a '0' to the GPIO-1 bit forces the GPIO-1 pin low.
When reading this bit, the digital value on the GPIO-1 pin is acquired.
GPIO-0 status bit.
Writing a '1' to the GPIO-0 bit puts the GPIO-1 pin into a Hi-Z state (default).
DB8 GPIO-0 1
Writing a '0' to the GPIO-0 bit forces the GPIO-1 pin low.
When reading this bit, the digital value on the GPIO-0 pin is acquired.
Disable SDO bit.
Set the DSDO bit to '0' to enable the SDO pin (default). The SDO pin works as a normal SPI output.
DB7 DSDO 0
Set the DSDO bit to '1' to disable the SDO pin. The SDO pin is always in a Hi-Z state regardless of the status of the CS
pin is.
No operation bit.
DB6 NOP 0 Writing '0' or '1' to this bit has no effect and the bit returns to '0' at the end of the write operation.
Reading the bit always returns '0'.
DAC-3 gain bit.
DB5 GAIN-3 1 Set the GAIN-3 bit to '1' for a gain = 4.
Set the GAIN-3 bit to '0' for a gain = 2.
DAC-2 gain bit.
DB4 GAIN-2 1 Set the GAIN-2 bit to '1' for a gain = 4.
Set the GAIN-2 bit to '0' for a gain = 2.
DAC-1 gain bit.
DB3 GAIN-1 1 Set the GAIN-1 bit to '1' for a gain = 4.
Set the GAIN-1 bit to '0' for a gain = 2.
DAC-0 gain bit.
DB2 GAIN-0 1 Set the GAIN-0 bit to '1' for a gain = 4.
Set the GAIN-0 bit to '0' for a gain = 2.
DB1:DB0 — 0 Reserved. Writing to these bits has no effect; reading these bits returns '0'.
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